Analysis and Design of Multi-Stacked FET Power Amplifier With Phase-Compensation Inductors in Millimeter-Wave Band

A Ku-Band Broadband Stacked FET Power Amplifier Using 0.15 μm GaAs pHEMT

“…The value of the gate capacitance ( C g ) is determined by the optimal load impedance of the lower transistors so that each transistor can produce the maximum voltage swing and the maximum output power. For design convenience, the calculation of the C g value is given below [ 21 ]. where C gs is the gate–drain parasitic capacitance, g m2 is the transconductance of the upper transistor [ 22 ], and R opt is the load impedance of the lower transistor.…”

“…In fact, the effect brought by the gate–source parasitic capacitance C gs2 of the upper transistor at lower frequencies cannot be simply ignored. Therefore, Z in is not a real impedance, and the imaginary part of Z in is very unfavorable for impedance matching in the broadband range [ 21 ].…”

“…The value of the gate capacitance (Cg) is determined by the optimal load impedance of the lower transistors so that each transistor can produce the maximum voltage swing and the maximum output power. For design convenience, the calculation of the Cg value is given below [21]. A single stacked FET B can reach a maximum output power of 29 dBm after load pull.…”

“…In fact, the effect brought by the gate-source parasitic capacitance Cgs2 of the upper transistor at lower frequencies cannot be simply ignored. Therefore, Zin is not a real impedance, and the imaginary part of Zin is very unfavorable for impedance matching in the broadband range [21]. A simple and effective way to achieve impedance matching between the upper transistor and the lower transistor is by introducing an inter-stage matching structure.…”