Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter

Tohidian, Massoud; Madadi, Iman; Staszewski, Robert Bogdan

doi:10.1109/jssc.2014.2359656

Cited by 70 publications

(88 citation statements)

References 25 publications

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“…A behavioral model of the Gm-cell-based pixel with charge-domain CDS is depicted in Figure 3. As two distinct filtering functions, namely, a continuous-time (CT) sinc low-pass filter H WI ( f ) [19] and a DT high-pass filter H CDS ( f ) are realized simultaneously, the overall transfer function of the charge-domain CDS can be written as

| H_{C D 2} (f) | = | H_{C D 1} (f) | \cdot | H_{C D S} (f) | = | 2 \frac{g_{m} T_{c h}}{C_{S / H}} s i n c (π f T_{c h}) \cdot s i n c (π f T_{Z O H}) \cdot s i n (π f T_{0}) |

…”

Section: Operating Principle and Implementation Of A Gm-cell-basedmentioning

confidence: 99%

Temporal Noise Analysis of Charge-Domain Sampling Readout Circuits for CMOS Image Sensors

Theuwissen

2018

Sensors

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This paper presents a temporal noise analysis of charge-domain sampling readout circuits for Complementary Metal-Oxide Semiconductor (CMOS) image sensors. In order to address the trade-off between the low input-referred noise and high dynamic range, a Gm-cell-based pixel together with a charge-domain correlated-double sampling (CDS) technique has been proposed to provide a way to efficiently embed a tunable conversion gain along the read-out path. Such readout topology, however, operates in a non-stationery large-signal behavior, and the statistical properties of its temporal noise are a function of time. Conventional noise analysis methods for CMOS image sensors are based on steady-state signal models, and therefore cannot be readily applied for Gm-cell-based pixels. In this paper, we develop analysis models for both thermal noise and flicker noise in Gm-cell-based pixels by employing the time-domain linear analysis approach and the non-stationary noise analysis theory, which help to quantitatively evaluate the temporal noise characteristic of Gm-cell-based pixels. Both models were numerically computed in MATLAB using design parameters of a prototype chip, and compared with both simulation and experimental results. The good agreement between the theoretical and measurement results verifies the effectiveness of the proposed noise analysis models.

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| H_{C D 2} (f) | = | H_{C D 1} (f) | \cdot | H_{C D S} (f) | = | 2 \frac{g_{m} T_{c h}}{C_{S / H}} s i n c (π f T_{c h}) \cdot s i n c (π f T_{Z O H}) \cdot s i n (π f T_{0}) |

…”

Section: Operating Principle and Implementation Of A Gm-cell-basedmentioning

confidence: 99%

Temporal Noise Analysis of Charge-Domain Sampling Readout Circuits for CMOS Image Sensors

Theuwissen

2018

Sensors

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“…At the end of , the sampled charge on is just shared with another capacitor. This mechanism can arbitrarily increase the IIR filter's order [19].…”

Section: A Bpf Unit Structurementioning

confidence: 99%

“…10). Therefore, we find the DT differential output noise PSD as (18) Since the absolute value of four input sources are the same, (18) can be simplified as (19) and by substituting , the differential output noise PSD is simplified to (20). (See equation at the bottom of the page.)…”

Section: B Dt Cs-bpf Noise Modelmentioning

confidence: 99%

Analysis and Design of I/Q Charge-Sharing Band-Pass-Filter for Superheterodyne Receivers

Madadi

Tohidian

Staszewski

2015

IEEE Trans. Circuits Syst. I

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A complex quadrature charge-sharing (CS) technique is proposed to implement a discrete-time band-pass filter (BPF) with a programmable bandwidth of 20-100 MHz. The BPF is part of a cellular superheterodyne receiver and completely determines the receiver frequency selectivity. It operates at the full sampling rate of up to 5.2 GHz corresponding to the 1.2 GHz RF input frequency, thus making it free from any aliasing or replicas in its transfer function. Furthermore, the advantage of CS-BPF over other band-pass filters such as N-path, active-RC, -, and biquad is described. A mathematical noise analysis of the CS-BPF and the comparison of simulations and calculations are presented. The entire 65 nm CMOS receiver, which does not include a front-end LNTA for test reasons, achieves a total gain of 35 dB, IRN of , out-of-band IIP3 of 10 dBm. It consumes 24 mA at 1.2 V power supply.

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“…Here, the following FOM [4], [21] is selected to evaluate the overall performance, (9) where N is the number of poles and is the normalized power consumption. The spurious-free dynamic range is given by , where is the IRN power.…”

Section: E Performance Comparisonmentioning

confidence: 99%

“…Although an antialiasing filter (AAF) is required (normally embedded into the mixer's RC load), SC solutions are competitive to reject the close-in adjacent/alternate channels. A real-pole SC LPF implementation [8] shows very low power (1.96 mW) and noise (2.85 nV/ Hz), being an attractive analog approach to partition the channel selection to the digital domain for power and area savings [9]. Regrettably, despite the used 7th-order, the lack of complex poles worsens the roll-off around the dB BW.…”

Section: Introductionmentioning

confidence: 99%

A 0.02 mm<formula formulatype="inline"><tex Notation="TeX">$^{2}$</tex></formula> 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad

Zhao¹,

Mak²,

Martins³

et al. 2015

IEEE J. Solid-State Circuits

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This paper reports a switched-capacitor (SC)-buffer Biquad that can be recycled efficiently as an ultra-compact low-pass filter (LPF) in nanoscale CMOS. It incorporates only passive-SC networks and open-loop unity-gain buffers; both are friendlier to technology downscaling than most conventional Biquads that use high-gain amplifiers and closed-loop negative feedback. Complex-pole pairs with independent Q factors are recursively realized in one clock period, while ensuring low crosstalk effect between the formations of each pole. Nonlinearity and parasitic effects are inherently low due to no internal gain. The fabricated 65 nm CMOS prototype is a 1x-recycling SC-buffer Biquad that is equivalent to a 4th-order Butterworth LPF with 75% buffer utilization. It occupies a die size of only 0.02 mm and exhibits 20x bandwidth tunability (0.5 to 10 MHz), linear with the clock rate. At 10 MHz bandwidth, the in-band IIP3 is +17.6 dBm and input-referred noise is 19.5 nV/ Hz; they correspond to 59.2 dB SFDR and 0.013 fJ figure-of-merit which are favorably comparable with the recent art. The 1 dB compression point conforms to the out-of-band blocker profile of the LTE standard at a 20 dB front-end gain. Index Terms-1 dB compression point , Butterworth, clock generator, CMOS, channel selection, clock-rate-defined bandwidth (BW), die area, figure-of-merit (FOM), low-pass filter (LPF), long-term evolution (LTE), operational transconductance amplifier (OTA), recycling, switched capacitor (SC), wireless radios.0018-9200

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Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter

Cited by 70 publications

References 25 publications

Temporal Noise Analysis of Charge-Domain Sampling Readout Circuits for CMOS Image Sensors

Temporal Noise Analysis of Charge-Domain Sampling Readout Circuits for CMOS Image Sensors

Analysis and Design of I/Q Charge-Sharing Band-Pass-Filter for Superheterodyne Receivers

A 0.02 mm<formula formulatype="inline"><tex Notation="TeX">$^{2}$</tex></formula> 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad

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