Analysis and Design of 4-to-1 Capacitor-Stacking Balancer for Stacked Voltage Domain

Abstract

This paper presents an alternative method for achieving more efficient and reliable DC-DC conversion and balancing operations for low-power applications in a stacked voltage domain. This work comprehensively analyzes the operating principles and power conversion loss of a proposed capacitorstacking balancing circuit at the system level. The analysis and design of the capacitor-stacking balancing circuit in the stacked voltage domain, including the time-domain operation, voltage equation, and dead-time effect, are explored and implemented. This study provides an opportunity to achieve a highly optimized system with high efficiency. A comprehensive analysis of efficiency at the system level shows the advantages and limitations according to each stacking method under a given system condition. Considering the redundancy issues of the previous method at system-level analysis, the capacitor-stacking balancing method is a preferable choice for low-power, high-reliability, and high-efficiency applications under light load conditions. This study also provides an analytical efficiency model under current imbalance, which is a notable difference from previous research and case studies concerning power converters. Prototype board with lithium-ion battery power and a core voltage of 0.825 V-a low-power application-was built to verify the proposed model and analysis. The experimental efficiency reached 94.9% at 20% of the maximum workload.