Analog sequential architecture for neuro-fuzzy models VLSI implementation

Moreno, Juan Manuel; Madrenas, Jordi; Alarcón, Enrique; Cabestany, Joan

doi:10.1007/bfb0020314

Cited by 6 publications

(1 citation statement)

References 9 publications

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“…[6][7][8][9], to our knowledge no study has been done up to now on generalization of the area-delay tradeoff. In this work, we consider two reported sequential realizations that emulate feedforward algorithms (MLP, RBF and Takagi-Sugeno -TSK-fuzzy controllers) for the recall phase.…”

Section: Introductionmentioning

confidence: 96%

Mixed-Signal Neuro-Fuzzy Processor Implementations: Sequential Architectures and Circuit-Level Description

Madrenas¹,

Alarcón²

2002

Series in Machine Perception and Artificial Intelligence

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Mixed-signal VLSI design provides a tradeoff between the fast and compact but fixed analog implementations of neuro/fuzzy feedforward algorithms and the programmable but area and power consuming digital counterparts. In this chapter, a sequentiality study of such systems is performed. Basic blocks for sequential mixed-signal neural and fuzzy computing are proposed, and two sequential example processors are described. Feedback from the designed processors and subcircuits allowed considering the technology constraints for analysis and extension to different sequentiality degrees. IntroductionIn this chapter, we introduce architecture analysis and guidelines to develop sequential analog processing circuits. By means of switched techniques and analog memory elements, analog sequential processing circuits can be designed. These techniques are applied to the development of mixed-signal neural and fuzzy processors. For this purpose, the characteristics, constraints and properties of analog circuits, that are very different from their digital counterparts, have to be taken into account. At the architectural level, starting from sequential architectures of neural and fuzzy models, a performance analysis in terms of area and speed as a function of the sequentiality -or parallelism-degree is developed.Efficiency in terms of silicon area occupancy versus computation performance (speed) is fundamental in autonomous intelligent systems. For 93 Neural Networks and Systolic Array Design Downloaded from www.worldscientific.com by MONASH UNIVERSITY on 04/23/17. For personal use only.

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Section: Introductionmentioning

confidence: 96%