Analog/RF Performance of Triple Material Gate Stack-Graded Channel Double Gate-Junctionless Strained-silicon MOSFET with Fixed Charges

Suddapalli, Subba Rao; Joseph, Rani Deepika Balavendran; Chintala, Vijaya Durga; Saramekala, Gopi Krishna; Srikar, D.; Rao, N. Bheema

doi:10.1007/s12633-021-01462-0

Cited by 5 publications

(3 citation statements)

References 24 publications

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“…All the notations are carried their usual meaning and calculated from [43][44][45][46]. Figure 11 analyses the comparison of f T with V fg for UAJDMDG, JDMDG and UAJDG structures.…”

Section: Resultsmentioning

confidence: 99%

Impact of underlap layer on DC and RF/analog performance of asymmetric junctionless dual material double gate MOSFET for low-power analog amplifier design

Basak,

Deyasi,

Sarkar

2024

Phys. Scr.

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Impact of underlap layer is analytically investigated on asymmetric junctionless dual material double gate MOSFET (AJDMDG) to reduce subthreshold slope and threshold voltage, which are two essential requirements with shrinking device dimensions to avoid short channel effects. The model utilizes two-dimensional Poisson’s equation with parabolic approximation for determining electrical parameters where dimensional ranges are kept within fabrication limit. Excellent accuracy is found for the obtained analytical outcome, when compared with results obtained from TCAD ATLAS simulator. Comparative study is extended for conventional junctionless DMDG (JDMDG) and underlap asymmetric junctionless single material DGFET (UAJDG) device, having identical dimensional parameters and biasing ranges; where the present structure exhibits superior performance in terms of threshold voltage, subthreshold slope and DIBL of 34.57%, 62.85% and 69.85% respectively compared to JDMDG and 12.50%, 26.08% and 40.25% respectively w.r.t UAJDG structure. Supremacy of the proposed architecture is further established with RF/analog Fig.ures of Merit (FOMs), which are essential for designing low power analog amplifier.

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“…All the notations are carried their usual meaning and calculated from [43][44][45][46]. Figure 11 analyses the comparison of f T with V fg for UAJDMDG, JDMDG and UAJDG structures.…”

Section: Resultsmentioning

confidence: 99%

Impact of underlap layer on DC and RF/analog performance of asymmetric junctionless dual material double gate MOSFET for low-power analog amplifier design

Basak,

Deyasi,

Sarkar

2024

Phys. Scr.

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“…This is because the performance and reliability of the device are degraded when hot electrons are injected between the gate and drain. Also, to minimize leakage current without significantly decreasing I on concentrations, the electric field strength close to the drain should be lowered to its smallest value [21].…”

Section: Introductionmentioning

confidence: 99%

An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation

Mudidhe,

Nistala

2023

Phys. Scr.

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The GAA FET has emerged as a promising device due to its excellent control over short-channel effects and improved electrostatic control. This manuscript presents the analytical modelling for the Dual Material Graded Channel (DMGC) Cylindrical GAA FET to characterize the drain current in linear, saturation, as well as subthreshold regions. The model incorporates the effect of supply voltage, radius, and thickness of oxide layer on the device enabling a comprehensive analysis of the device behaviour. The influence of subthreshold swing is also presented. Next, the analysis is extended to investigate the important analog performance parameters that includes transconductance and output conductance. The validation of the analytical model across a wide range of operating conditions with the simulated data is performed and observed to be a close match. Building upon the insights gained from the analytical modelling, a common source amplifier based on the DMGC CGAA FET is designed. The amplifier's performance has been optimized by carefully selecting the biasing conditions and a maximum gain value of 7.745 is achieved. Further, an improvement of 42.28% in output voltage is observed for DMGC in comparison with SMGC making it a promising device for high-performance integrated circuit design.

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“…These factors encompass distinct dielectrics 27 , gate length, gate oxide material, and gate oxide thickness 28 , along with considerations of the underlap effect 29 and vacancy defects 30 . Another avenue to enhance analog/RF performance involves the adoption of triple-material gates 31 . Nevertheless, there remains considerable room for further research to optimize analog/RF parameters, and the capability to interchange and fine-tune these parameters is crucial in analog circuit design to pinpoint the most suitable operating region.…”

mentioning

confidence: 99%

Trade-off analysis between gm/ID and fT of GNR-FETs with single-gate and double-gate device structure

Ahmad,

Kumar,

Mech

et al. 2024

Sci Rep

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This study examines the operational parameters of field-effect transistors (FETs) using single-gate (SG) and double-gate (DG) graphene nanoribbons (GNRs) within the analog/RF domain. A detailed exploration is conducted through an atomistic pz orbital model, derived from the Hamiltonian of graphene nanoribbons, employing the nonequilibrium Green’s function formalism (NEGF) for analysis. The atomic characteristics of the GNRFETs channel are accurately described by utilizing a tight-binding Hamiltonian with an atomistic pz orbital basis set. The primary focus of the analysis revolves around essential analog/RF parameters such as transconductance, transconductance generation factor (TGF), output resistance, early voltage, intrinsic gain, gate capacitance, cut-off frequency, and transit time. Furthermore, the study assesses the gain frequency product (GFP), transfer frequency product (TFP), and gain transfer frequency product (GTFP) to evaluate the balance between transistor efficiency, gain, and cut-off frequency. The research outcomes indicate that double-gate GNRFETs exhibit superior analog/RF performance in comparison to their single-gate counterparts. However, both types of devices demonstrate cut-off frequencies in the gigahertz range. The extensive data presented in this study provides valuable insights into the characteristics of SG and DG GNRFETs, particularly in terms of the figure-of-merit (FoM) for analog/RF performance, offering a comprehensive analysis of the trade-offs in analog applications. In addition, the analysis has been extended be performing a high-performance hybrid 6T static random-access memory (SRAM) to get the impact in their circuit level variation as well as improvement in their circuit performance.

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Analog/RF Performance of Triple Material Gate Stack-Graded Channel Double Gate-Junctionless Strained-silicon MOSFET with Fixed Charges

Cited by 5 publications

References 24 publications

Impact of underlap layer on DC and RF/analog performance of asymmetric junctionless dual material double gate MOSFET for low-power analog amplifier design

Impact of underlap layer on DC and RF/analog performance of asymmetric junctionless dual material double gate MOSFET for low-power analog amplifier design

An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation

Trade-off analysis between gm/ID and fT of GNR-FETs with single-gate and double-gate device structure

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