Analog Performance and its Variability in Sub-10 nm Fin-Width FinFETs: a Detailed Analysis

Abstract

This paper discusses in detail the effects of Sub-10nm fin-width (W fin ) on the analog performance and variability of FinFETs. It is observed through detailed measurements that the transconductance degrades and output conductance improves with the reduction in fin-width. Through different analog performance metrics, it is shown that analog circuit performance, in Sub-10nm W fin regime, cannot be improved just by W fin scaling but by optimizing source/drain resistance, gate dielectric thickness together with the W fin scaling. We also explored the effect of process induced total and random variability on trans-conductance and output conductance of FinFETs. A systematic strategy to decouple different variability sources has been discussed and it is shown that mobility, source/drain resistance and oxide thickness are the critical parameters to reduce variability.

Enhancement of Carrier Mobility in Semiconductor Nanostructures by Carrier Distribution Engineering

“…To look insight into the effect of gate configuration, we first study Ψ(z) in a 6.5 nm (10 layer) thick MoS2 channel under varied SG and DG configurations, where the channel is encapsulated by two 10 nm thick dielectrics with a εr of 10 and the both dielectrics are covered with metallic gates. Figure 1a shows Ψ(z) of channel electrons at ns = 5×10 12 cm −2 and corresponding potential profile V(z) of the device under the SG configuration. In such a configuration, the channel and top gate (TG) are electrically grounded while the bottom gate (BG) is biased with a positive voltage VBG, as shown in the inset.…”

“…[5][6][7] In addition to the merit of atomic thickness that is favorable for enhancing gate electrostatic control, [8][9][10][11] the self-saturated surfacial atomic structure represents another important advantage superior to silicon for attaining high device performance by suppressing extrinsic charge scattering events. [11][12][13][14] Even though 2D semiconductor FETs have been widely investigated, [15][16][17][18][19] pertinent physical studies regarding the impacts of device parameters and gate configuration on the fundamental envelope function 𝛹 (𝑧), which determines the distribution of electrons in the ultrathin channels of 2D FETs, or on the carrier mobility remained insufficient.…”

Optimizing U-Shape FinFETs for Sub-5nm Technology: Performance Analysis and Device-to-Circuit Evaluation in Digital and Analog/Radio Frequency Applications

“…It is noticed that increasing the W U-fin enhances the I on attributed to the increase in effective width (I d α W eff ). 29 Furthermore, increasing the W U-fin leads to a decrease in source/drain resistance, an increase in carrier density, and a decrease in carrier scattering 40 is also one of the reasons contributing to the increase in I on . The I off also increases with W U-fin due to poor gate control over the channel, resulting in SCEs.…”

“…Figure 8c displays the effect of W U-fin on both SS and I on /I off ratio. The SS increases due to inadequate gateelectrostatic control, 40 while I on /I off decreases significantly due to the increase in I off . Figure 9a visualizes the plots of g m and g ds with variations in W U-fin .…”