Analog performance and application of graded-channel fully depleted SOI MOSFETs

Silicon on Insulator Technology Review

“…• [23,14,43]Today we are settling everything in small area .When scaling down the device dimensions the doping densities must be increased to maintain proper device behaviour, [74,64,108] which is hard to manage when the device dimensions reach 50 nm and below. However, for thin film devices, such as fully depleted SOI, the doping densities required are lower.…”

Two-dimensional analytical subthreshold model of graded channel DG FD SOI n-MOSFET with gate misalignment effect

“…Furthermore, a GC device has not been analyzed so far and the research on UD DG devices has mainly focused on short channel effects and charge control [5,6]. Recently, ''laterally asymmetric channel'' devices also known as Graded Channel (GC) DG-MOSFET have been reported [7][8][9][10], to overcome problems such as (a) hot electron degradation, (b) threshold voltage roll-off and (c) parasitic bipolar effects, exhibited by uniformly doped (UD) DG devices. The GC SOI MOSFET is an asymmetric channel device, which was initially introduced to minimize bipolar effects in FD transistors [11].…”

Channel Length Influence on the Performance of Source-Follower Buffers Implemented with Graded-Channel SOI nMOSFETs

“…However, standard FD SOI transistor presents inherent parasitic bipolar effects, which cause the breakdown voltage reduction and increase of output conductance (g D ), degrading the analog performance of SOI transistors. Aiming to improve the SOI device analog characteristics, an asymmetric channel device, so-called Graded-Channel (GC) SOI nMOSFET has been proposed (8). In this device a region of length L LD is kept with the natural wafer doping concentration, while the threshold voltage (V T ) implantation is performed at the source side only.…”