Analog IC Reliability in Nanometer CMOS

Charge-based stochastic aging analysis of CMOS circuits

“…In order to overcome this disadvantage an analog behavioral model including degradation, process variation and environmental influences is needed. The presented extended technology-independent BSIM6 model can be used to inves tigate the impact of degradation due to Hot Carrier Injection (HCI) and Bias Temperature Instability (BTl) [2] . Moreover, any circuit can easily be simulated using this model to estimate the age-dependent yield on circuit level.…”

Review of Polynomial Chaos-Based Methods for Uncertainty Quantification in Modern Integrated Circuits

“…In general, two main types of uncertainty sources affect the behavior of modern ICs: temporal and spatial [26]. The first are time-dependent effects, which can be divided into wearout or aging, which permanently degrade the circuit performance over time (e.g., hot carrier injection), and transient disturbances, which manifest only for a limited period of time and, usually, do not permanently deteriorate the circuit performance (such as electromagnetic interference).…”

“…In this scenario, excluding systematic or epistemic uncertainty sources (which are uncertainties due to a lack of knowledge), the device-related sources of spatial unreliability can be described as random [26] and can be characterized in a statistical way. Hence, the process-induced variations can be represented by considering the geometrical (i.e., the width and length of an interconnection and the thickness of a dielectric material) or electrical (i.e., the threshold voltage of a transistor and the relative permittivity of the substrate) parameters of the device under study as random variables with a suitable distribution.…”

“…Spatial variability, instead, is caused by the fabrication process of modern ICs: its effects manifest immediately after production and are fixed over time. In particular, spatial uncertainty effects can be divided into two categories: the ones causing a mismatch (intradie variations) between devices on the same die that are designed to be identical, and the interdie ones causing variations between devices separated by a long distance (from die to die) or that are manufactured at a different time (between wafer to wafer, or lot to lot) [26]. Typically, interdie variations cause a shift in the mean value of the chosen design parameters [26], while process-induced mismatch significantly threatens the efficiency of digital circuits, by influencing their timing closure [8], and analog ones, since matched devices and differential signal paths are fundamental for most high-performance analog circuits [27].…”

On improving dependability of analog and mixed-signal SoCs

“…HCI occurs when an "electron" or "hole" gains sufficient kinetic energy to overcome a potential barrier and breaks the interface state in MOS devices. These charge carriers can become trapped in the gate dielectric and hence permanently change the transistor characteristics [Mar13,Wik14c]. Therefore, HCI will degrade the electrical characteristics of MOSFETs and hence the dependability of associated electronic systems.…”