Analog Design for a Power Transmission Line Sensing and Analysis VLSI Chip

MacLean, E.; Jain, V.K.

doi:10.1109/dft.2010.58

Cited by 5 publications

(2 citation statements)

References 11 publications

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“…Frontend Defect Tolerance: this was discussed in [1], therefore a detailed discussion is not presented here. Suffice it to say that incorporation of multiple frontends, the yield improves to 0.9999.…”

Section: Bk 4078mentioning

confidence: 98%

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A Power Transmission Line Fault Distance Estimation VLSI Chip: Design and Defect Tolerance

MacLean

Jain

2011

2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

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This paper 1 presents a system-on-a-chip for fault detection and fault-distance-estimation for power transmission lines in the smart grid. Toward this goal we have designed and fabricated three chips: PGS4, PGS5 and PGS6, each successively more advanced than the previous one. PGS4 and PGS5 each have two spiral sensors, of which one is dedicated to sensing the transmission line current, and the other serves as a redundant sensor (in case of defects on the primary one), but also as a transmission line emulator in the test phase. In this latter role, i.e., as driver, a new model for the coupled coils is proposed. These chips seek to implement an advanced fault distance estimation algorithm proposed by Radojevic which utilizes frequency domain measurements of the transmission line voltages and currents. Specifically, the fault distance is estimated using the Fourier coefficients of the fundamental and third harmonic in an algebraic formula. PGS5 and PGS6 are able to perform this analysis, with some differences as delineated in the paper. The sensor spiral feeds into a high gain amplifier and a source follower, termed as the frontend, which is the key to the operation of the chip. Therefore three copies, actually variations, of the frontend, selectable with a multiplexer, are provided for defect tolerance. For the Fourier analysis needed for fault distance estimation, we have used a powerful digital macro, MA_PLUS, which has been presented in our previous papers. We have successfully tested PGS4, and some test results are included for PGS5. Test results for PGS6 will be presented at the conference. As stated earlier, these designs are successively more advanced with a view toward enhancing the probability of success of the final design. Results for defect tolerance for the coils and the frontends are included in the paper.

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Section: Bk 4078mentioning

confidence: 98%

“…(The acronym PGS stands for Power Grid Sensor.) Considerable interest currently exists in the use of distributed and dedicated VLSI chips for the sensing and control of power systems [1]- [8], potentially resulting in a smart grid.…”

Section: Introductionmentioning

confidence: 99%

A Power Transmission Line Fault Distance Estimation VLSI Chip: Design and Defect Tolerance

MacLean

Jain

2011

2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

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Massively Deployable Intelligent Sensors for the Smart Power Grid

Jain

Chapman

2010

2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems

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Enhanced Defect Tolerance through Matrixed Deployment of Intelligent Sensors for the Smart Power Grid

Jain

Chapman

2011

2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

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We have recently proposed 3-D intelligent sensors for the power grid with a view toward helping improve its reliability and restoration capability. Our solution is to use a matrix of fault tolerant distributed sensors that can sense as well as take local actions. These new sensors are "3-D Heterogeneous Sensor System on a Chip (HSoC)", which can potentially overcome delays and domino effects. The paper 1 specifically focuses on the application of the 3-D HSoCs for fault-distance estimation and the issues involved in the failure of such devices -due to defects both within the chip and due to external stress. We show that the use of multiple devices brings benefits relating to both the detection and accuracies of fault distance and arc voltage estimates. Specifically, if the nearest device is located at -x relative to the location of the transmission line fault, then the use of additional devices at -D-x, D-x, and 2D-x diminishes the probability of loss of detection considerably. The paper presents studies on this fault tolerance, as well as accuracy of estimation, vs. the number of devices used for collaborative detection. It is important to note that this collaboration does not require additional sensors, only communication among them. Matrixed HSoCs can provide several fold improvement over single HSoC.Keyword -: Smart power grid, 3-D HSoC sensors, matrixed deployment, power grid fault detection and distance estimation, defect and fault tolerance I. INTRODUCTION Electrical power grids are moving from the era of a few larger centralized power sources to one which combines these traditional systems with widely distributed green power sources. These new energy sources, such as solar and wind power, cover large geographic, often remote, areas with long transmission line connections. Due to their dependence on local environmental conditions they have considerably less predictability and control in their power generation. This combination of new challenges points to the need for the addition of smart sensors on the power grid to enhance system reliability, fault tolerance, stability and control.The underlying goal of this research is to improve the reliability and restoration capability of wide area Power Grids (PG) thereby reducing power outages and their cascade effects. Our solution is to embed novel intelligent sensors with distributed processing tools to provide real time control and monitoring of PGs from transmission and distribution levels. Our sensors will provide accurate information to protective relays, enable intelligent islanding, a means by which the modeling of loads can be based upon accurate measured data rather than estimated data for load shedding. Since power networks must be highly reliable this requires the creation of redundant and reliable systems in both the individual sensors and interaction between the sensors. The unique sensor architecture, fabrication, and signal processing issues are addressed through a "3-D Heterogeneous Sensor System on a Chip (HSoC)". While technologically and scient...

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Analog Design for a Power Transmission Line Sensing and Analysis VLSI Chip

Cited by 5 publications

References 11 publications

A Power Transmission Line Fault Distance Estimation VLSI Chip: Design and Defect Tolerance

A Power Transmission Line Fault Distance Estimation VLSI Chip: Design and Defect Tolerance

Massively Deployable Intelligent Sensors for the Smart Power Grid

Enhanced Defect Tolerance through Matrixed Deployment of Intelligent Sensors for the Smart Power Grid

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