2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems 2011
DOI: 10.1109/dft.2011.40
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Enhanced Defect Tolerance through Matrixed Deployment of Intelligent Sensors for the Smart Power Grid

Abstract: We have recently proposed 3-D intelligent sensors for the power grid with a view toward helping improve its reliability and restoration capability. Our solution is to use a matrix of fault tolerant distributed sensors that can sense as well as take local actions. These new sensors are "3-D Heterogeneous Sensor System on a Chip (HSoC)", which can potentially overcome delays and domino effects. The paper 1 specifically focuses on the application of the 3-D HSoCs for fault-distance estimation and the issues invol… Show more

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Cited by 4 publications
(3 citation statements)
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“…Most importantly, as stated earlier one of the frontends is located inside the coils, which allows evaluation of the interference generated though inductive coupling. Further discussion on defect tolerance based on the use of multiple SoC chips in provided in a companion paper [3].…”
Section: Bk 4078mentioning
confidence: 99%
See 1 more Smart Citation
“…Most importantly, as stated earlier one of the frontends is located inside the coils, which allows evaluation of the interference generated though inductive coupling. Further discussion on defect tolerance based on the use of multiple SoC chips in provided in a companion paper [3].…”
Section: Bk 4078mentioning
confidence: 99%
“…Table 1 compares the results obtained from the chip with those of esim simulation and theory, thus further validating the Fourier series analysis at the chip. Fault Distance: Once the Fourier coefficients are known, the fault distance is calculated in the FDA using equation (3). In this SoC chip the numerator (that is the difference of the voltage coefficients) is assumed to be j, i.e., purely imaginary with a weight of 1.…”
Section: Bk 4078mentioning
confidence: 99%
“…For the past decade there has been an increased focus on 3D Heterogeneous Systems on a Chip (3D-HSoC) [222][223][224][225][226][227][228][229][230][231][232][233][234][235] and an explosion of wearable devices that carry a lot of personal information [236][237][238][239][240][241][242][243][244][245][246][247][248]. These chips are custom-produced in small quantities and hence carefully controlled.…”
Section: Integrity Solutions For Systems On a Chipmentioning
confidence: 99%