Analog Architecture Complexity Theory Empowering Ultra-Low Power Configurable Analog and Mixed Mode SoC Systems

Abstract

This discussion develops a theoretical analog architecture framework similar to the well developed digital architecture theory. Designing analog systems, whether small or large scale, must optimize their architectures for energy consumption. As in digital systems, a strong architecture theory, based on experimental results, is essential for these opportunities. The recent availability of programmable and configurable analog technologies, as well as the start of analog numerical analysis, makes considering scaling of analog computation more than a purely theoretical interest. Although some aspects nicely parallel digital architecture concepts, analog architecture theory requires revisiting some of the foundations of parallel digital architectures, particularly revisiting structures where communication and memory access, instead of processor operations, that dominates complexity. This discussion shows multiple system examples from Analog-to-Digital Converters (ADC) to Vector-Matrix Multiplication (VMM), adaptive filters, image processing, sorting, and other computing directions.

A Cluster of FPAAs to Recognize Images Using Neural Networks

“…As the 28 × 28 input image would be input serially, typical of outputs of imaging devices (Fig. 6), the DCT image-compression would utilize a simplified image convolution [4] on a single SoC FPAA. Although the number of CABs requires some research and implementation, this algorithmic step likely requires 10-20 (Fig.…”

Physical Computing: Unifying Real Number Computation to Enable Energy Efficient Computing

“…As mentioned above, the coefficient for computational energy efficiency, the energy or power required per operation, decreases by typically 1000× an equivalent digital computation, while the scaling metric in O(•) remains unchanged. Some aspects might improve the polynomial or similar function inside of O(•) say by architectural improvements in the physical computing structure (e.g., [14]). This effort affirms these improvements in energy efficiency, and builds upon these opportunities in energy efficiency by discussing the possibility to significantly change the scaling dependency characterized by O(•) for physical computing systems because of the different computing capabilities enabled by providing a model and framework to explore these opportunities.…”

“…Recently, analog computation has developed a framework (Figure 1) that includes analog numerical analysis techniques [16], analog algorithm complexity theory [14], and analog algorithm abstraction theory [17]. Current programmable Analog design is no longer seen as numerically inferior to digital computation [16], or seen as too complex to have levels of abstraction like digital computation [17], or seen to be governed by digital processor techniques where it rather now pushes the questions for both analog and digital architecture questions [14]. Analog computation becomes relevant with the advent of programmable and configurable FPAA devices [18,19] and the associated design and synthesis tools [20,21] incorporating parts of this framework.…”

“…Some examples in P A improve P D algorithms, although remain in P A (Figure 13). Spaghetti sort [67] solved using analog WTA networks [14] in O(M) time rather than greater than O(Mlog M) time for physical digital implementations. Grover's quantum computing algorithm also improved the O(•) time for the related algorithms [36].…”

Face Recognition on a Smart Image Sensor Using Local Gradients

“…Fine-grained parallelism can improve the execution time, lower the latency, reduce the amount of memory required to store temporary results, and maximize throughput [ 36 , 37 ]. Moreover, when the smart pixel operates in the analog domain, they can also reduce power consumption and die area [ 40 ].…”