Analog and RF modeling of FDSOI UTBB MOSFET using Leti-UTSOI model

Ghouli, Salim El; Scheer, P.; Minondo, M.; Juge, André; Poiroux, T.; Sallese, J.-M.; Lallement, Christophe

doi:10.1109/mixdes.2016.7529697

Cited by 8 publications

(6 citation statements)

References 21 publications

(19 reference statements)

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“…For a back gate voltage of 2 V, a maximum transconductance efficiency is obtained at IC = 4 in Fig. 6 where fT.gm/ID figure of merit found to be optimal [5] [23]. On the one hand, enhanced volume mobility helps to regain transconductance efficiency when back channel is inverted first (high VbG) with lower front capacitance.…”

Section: Discussionmentioning

confidence: 99%

“…To check how sensitive transconductance efficiency versus inversion coefficient chart is to manufacturing process variations, foundry process based UTSOI model [23], has been used to plot three normalized transconductance efficiency characteristics versus IC. The characteristics correspond to the typical (TT), fast (FF) and slow (SS) corners.…”

Section: E Sensitivity To Manufacturing Process Variationsmentioning

confidence: 99%

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Experimental ${g}_{m}/{I}_{{D}}$ Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET

Ghouli

Rideau

Monsieur

et al. 2018

IEEE Trans. Electron Devices

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Transconductance efficiency (gm/ID) is an essential design synthesis tool for low-power analog and RF applications. In this paper, the invariance of gm/ID versus normalized drain current curve is analyzed in an asymmetric double gate fully depleted MOSFET. The paper studies the breakdown of this invariance versus back gate voltage, transistor length, temperature, drain to source voltage and process variations. The unforeseeable invariance is emphasized by measurements of a commercial 28 nm UTBB FDSOI CMOS technology, thus supporting the gm/ID based design methodologies usage in double gate FDSOI transistors sizing.

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Section: Discussionmentioning

confidence: 99%

Section: E Sensitivity To Manufacturing Process Variationsmentioning

confidence: 99%

Experimental ${g}_{m}/{I}_{{D}}$ Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET

Ghouli

Rideau

Monsieur

et al. 2018

IEEE Trans. Electron Devices

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“…The classical hand calculation sizing methods are still based on inaccurate and questionable concepts such as the gate voltage overdrive (Vov = VGS -VTH, where VTH is the threshold voltage), and pessimistic rules of thumb such as the shortest possible length for higher fT, higher Vov constraint, and a maximum operation frequency of fT/10. Design in Moderate Inversion has become attractive in advanced technologies as it offers the optimum trade-off between speed, transconductance, and power consumption [9] [10]. However, the classical gate voltage overdrive is becoming a poor metric for MOSFET inversion level assessment in advanced technologies as it is based on conflicting definitions of the threshold voltage [11].…”

Section: Classical Design Sizing Methods In Analog and Rfmentioning

confidence: 99%

Analog RF and mm-Wave design Tradeoff in UTBB FDSOI: Application to a 35 GHz LNA

Ghouli

Grabinski²,

Sallese

et al. 2018

2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES)

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The state-of-the art RF and millimeter-wave firstcut circuits design requires simple hand calculation methods to avoid time-consuming iterative simulations. The classical MOSFET sizing methods used in advanced technologies, still rely on questionable and inaccurate concepts. Moreover, the pessimistic rules of thumb proposed for older bulk technologies are no more useful and lead to overdesign. This work takes advantage of the Moderate Inversion and uses low and high frequency figures of merit to provide a convenient sizing method for a 35 GHz Low Noise Amplifier (LNA) in 28 nm UTBB FDSOI technology.

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“…Fig. 13 depicts the envisioned cryogenic electrical interface chain for silicon qubits [155] and relates what the CEA-Leti group has already published [156]- [165].…”

Section: ) Research At Cea-letimentioning

confidence: 98%

CMOS Integrated Circuits for the Quantum Information Sciences

Anders

Babaie

Bardin

et al. 2023

IEEE Trans. Quantum Eng.

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Over the past decade, significant progress in quantum technologies has been made and, hence, engineering of these systems has become an important research area. Many researchers have become interested in studying ways in which classical integrated circuits can be used to complement quantum mechanical systems, enabling more compact, performant, and/or extensible systems than would be otherwise feasible. In this article-written by a consortium of early contributors to the field-we provide a review of some of the early integrated circuits for the quantum information sciences. CMOS and BiCMOS integrated circuits for nuclear magnetic resonance, nitrogen-vacancy-based magnetometry, trapped-ion-based quantum computing, superconductor-based quantum computing, and quantum-dot based quantum computing are described. In each case, the basic technological requirements are presented before describing proof-of-concept integrated circuits. We conclude by summarizing some of the many open research areas in the quantum information sciences for CMOS designers.

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Analog and RF modeling of FDSOI UTBB MOSFET using Leti-UTSOI model

Cited by 8 publications

References 21 publications

Experimental ${g}_{m}/{I}_{{D}}$ Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET

Experimental ${g}_{m}/{I}_{{D}}$ Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET

Analog RF and mm-Wave design Tradeoff in UTBB FDSOI: Application to a 35 GHz LNA

CMOS Integrated Circuits for the Quantum Information Sciences

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