Analog and digital approaches for an energy efficient low complexity channel decoder

A 3μW 500 kb/s ultra low power analog decoder with digital I/O in 65 nm CMOS

“…To mitigate mismatch effects in the analog decoding cores, one and two-dimensional common centroid layout techniques were applied throughout the circuits. NMOS transistor dimensions (W/L) were selected as 6.0/0.5 µm following approximate simulations presented in [5]. However, while designing the layout it appeared that uniform dimensions for all transistors result in unused spaces in the layout.…”

“…Since analog decoding circuits even for the most simple codes can easily include several thousands of transistors, the required Monte-Carlo simulation for accurate BER evaluation is not practical. Therefore, simulation of analog decoders has been usually performed through over-simplified methods such as statistical analysis [4], [5]. Such simulations can only offer a rough estimate of the circuit performance and help to modify the critical design factors.…”

“…Precise evaluation of these decoding circuits is best to be performed by chip measurements. Following the background theory and architecture description that have been reported in [6] and follow up simulations that has been performed in [7], [5] to cope with technical challenges and choose design parameters, an analog decoder was eventually fabricated in 65 nm CMOS technology. Here, the measurement results are presented to conclude the work.…”