A 3μW 500 kb/s ultra low power analog decoder with digital I/O in 65 nm CMOS

Abstract

Measurement results of an analog channel decoder in 65 nm CMOS are presented. We target ultra compact and low power applications with low to medium throughput requirements. The decoding core is designed for (7,5)8 convolutional codes and takes 0.104 mm 2 on silicon. The degrading effects of analog imperfections are investigated and the presented results allow power, performance and throughput trade-offs. Analyzing the bit error rate (BER) performance under extreme power constraints provides insights on energy efficiency and limitations of small scale analog decoders. For the limited power budget of 3 µW the decoder performs the required computations to provide 1 dB of coding gain at BER=0.001 for 500 kb/s throughput. The presented chip has digital I/O that facilitates embedding it in a conventional digital receiver.

Low Power Analog and Digital (7,5) Convolutional Decoders in 65 nm CMOS

“…For the analog decoders, however, the power and energy figures include the current of the CS-DACs, since this passes through the decoding cores. Power consumption of the digital interface of the analog decoding circuits is provided in an earlier publication [35], where measurement results of the first analog decoder, AD1, are also presented.…”

“…When a complete block has been buffered, it is applied in parallel to the decoding core via an array of 4-bit CS-DACs, for which details are given in [35]. The decoding core works on these data, represented by currents, and generates 14 differential decoded soft output bits.…”