An Unassisted, Low Trigger-, and High Holding-Voltage SCR (uSCR) for On-Chip ESD-Protection Applications

Lou, Lifang; Liou, J.J.

doi:10.1109/led.2007.909838

Cited by 20 publications

(4 citation statements)

References 7 publications

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“…Various researches have been carried out based on the conventional ESD protection structures such as diode, metal-oxide-semiconductor (MOS) and silicon controlled rectifier (SCR). [2][3][4][5][6][7][8][9] The diode [2] and gate-grounded NMOS (GGNMOS) [3] are attractive because of their small snapback margin. However, they have poor ESD robustness [4] and need large chip area to reach the required ESD protection level, [5] resulting in the increasing cost.…”

Section: Introductionmentioning

confidence: 99%

“…However, they have poor ESD robustness [4] and need large chip area to reach the required ESD protection level, [5] resulting in the increasing cost. The SCR is usually regarded as a promising ESD protection device due to its strong ESD robustness per unit area [6] and small parasitic effect, [7] whereas it is restrained from wide applications due to the high trigger voltage (V t1 ) [8] and low holding voltage (V h ), [9] which may result in the breakdown or latch-up of protected circuits.…”

Section: Introductionmentioning

confidence: 99%

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Design of a novel high holding voltage LVTSCR with embedded clamping diode*

Zhu

Liang

et al. 2020

Chinese Phys. B

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In order to reduce the latch-up risk of the traditional low-voltage-triggered silicon controlled rectifier (LVTSCR), a novel LVTSCR with embedded clamping diode (DC-LVTSCR) is proposed and verified in a 0.18-μm CMOS process. By embedding a p+ implant region into the drain of NMOS in the traditional LVTSCR, a reversed Zener diode is formed by the p+ implant region and the n+ bridge, which helps to improve the holding voltage and decrease the snapback region. The physical mechanisms of the LVTSCR and DC-LVTSCR are investigated in detail by transmission line pulse (TLP) tests and TCAD simulations. The TLP test results show that, compared with the traditional LVTSCR, the DC-LVTSCR exhibits a higher holding voltage of 6.2 V due to the embedded clamping diode. By further optimizing a key parameter of the DC-LVTSCR, the holding voltage can be effectively increased to 8.7 V. Therefore, the DC-LVTSCR is a promising ESD protection device for circuits with the operation voltage of 5.5–7 V.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design of a novel high holding voltage LVTSCR with embedded clamping diode*

Zhu

Liang

et al. 2020

Chinese Phys. B

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show abstract

“…To reduce the trigger voltage of the ESD protection structures, in some designs, ESD implantations have been added, and the ESD robustness can be significantly improved [5,6] . However, the fabrication cost of an IC is also increased due to the additional mask layers and process steps.…”

Section: Introductionmentioning

confidence: 99%

Ultra-low-voltage-trigger thyristor for on-chip ESD protection without extra process cost

2009

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A new thyristor is proposed and realized in the foundry's 0.18-µm CMOS process for electrostatic discharge (ESD) protection. Without extra mask layers or process steps, the new ultra-low-voltage-trigger thyristor (ULVT thyristor) has a trigger voltage as low as 6.7 V and an ESD robustness exceeding 50 mA/µm, which enables effective ESD protection. Compared with the traditional medium-voltage-trigger thyristor (MVT thyristor), the new structure not only has a lower trigger voltage, but can also provide better ESD protection under both positive and negative ESD zapping conditions.

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“…Among these typical ESD protection devices, many engineers prefer the silicon-controlled rectifier (SCR) owing to its high current density. Additionally, various studies have attempted to improve the electrical characteristics of SCR with various Si materials [12]- [15]. However, SiC has a critical electric field that is 10 times larger than that of Si, whereas its forward voltage drop is only approximately 3 times that of Si [16].…”

mentioning

confidence: 99%

Design of 4H-SiC-Based Silicon-Controlled Rectifier With High Holding Voltage Using Segment Topology for High-Voltage ESD Protection

Lee

Kim

et al. 2020

IEEE Electron Device Lett.

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In this letter, a new silicon-controlled rectifier (SCR) structure fabricated using 4H-SiC materials has been proposed and investigated. The proposed structure alleviates the strong-snapback phenomenon that occurs in the 4H-SiC SCR and demonstrates low trigger voltage and high holding voltage characteristics. The proposed device exhibits improved snapback characteristics with very high holding voltage against electrostatic discharge surges owing to the structural features and application of segment topology. It also has excellent on-resistance and improved thermal reliability owing to the physical characteristics of 4H-SiC. Traditional SCR and low-voltage trigger SCR (LVTSCR) are fabricated with 4H-SiC under the same conditions and their electrical characteristics are comparatively analyzed with those of the proposed SCR. This study also evaluates the electrical characteristics at high temperatures (300-500 K) to verify the high-temperature reliability of the proposed structure.

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An Unassisted, Low Trigger-, and High Holding-Voltage SCR (uSCR) for On-Chip ESD-Protection Applications

Cited by 20 publications

References 7 publications

Design of a novel high holding voltage LVTSCR with embedded clamping diode*

Design of a novel high holding voltage LVTSCR with embedded clamping diode*

Ultra-low-voltage-trigger thyristor for on-chip ESD protection without extra process cost

Design of 4H-SiC-Based Silicon-Controlled Rectifier With High Holding Voltage Using Segment Topology for High-Voltage ESD Protection

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