An ultralow-energy adc for smart dust

Scott, M.D.; Boser, Bernhard E.; Pister, Kristofer S. J.

doi:10.1109/jssc.2003.813296

Cited by 245 publications

(132 citation statements)

References 11 publications

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“…Step control unit ignites the set signal to DAC control unit which sends a sample signal to the DAC in the second step (2). The MSB output of the DAC drives comparator.…”

Section: Asynchronous Controlmentioning

confidence: 99%

“…The successive approximation register (SAR) type analog-to-digital converter (ADC) is widely used in autonomous sensor system and/or in portable sensory system for its low power consumption with a sampling rate ranging from a few KHz to tens of MHz [1][2][3][4][5]. Low power consumptions are caused by its simple hardware that requires only a comparator, a capacitor array and digital logic.…”

Section: Introductionmentioning

confidence: 99%

“…Biomedical applications such as ECG (electro cardiogram) and EEG (electroencephalogram) generally employed a SAR type ADC for its low signal frequency with high accuracy. Especially in handheld or portable medical devices for EEG and ECG signal detection, the high resolution with low power SAR type ADC is highly required [2][3][4]. Since the SAR type ADC is generally implemented with the capacitor array, it requires large chip area, if it is implemented with direct binary weighted capacitor array in high resolution applications (>10 bits).…”

Section: Introductionmentioning

confidence: 99%

“…The conversion requires 12 clock periods of the main clock; the first period is for the input sampling and next 11 periods are for remaining successive approximation cycles. During the input sampling, the MSB can be determined as in the reference [1][2][3][4]. Therefore, we need the 11-bit array of capacitors just for remaining 11-bit successive conversion, which means that the overall capacitors are reduced to one half compared to those of conventional direct implementation that requires 12 successive conversion steps excluding sampling periods.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A 12-b Asynchronous SAR Type ADC for Bio Signal Detection

Lim¹,

Kim²,

Yoon³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper describes a low power asynchronous successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for biomedical applications in a 0.35 µm CMOS technology. The digital-to-analog converter (DAC) uses a capacitive split-arrays consisting of 6-b main array, an attenuation capacitor C and a 5-b sub array for low power consumption and small die area. Moreover, splitting the MSB capacitor into subcapacitors and an asynchronous SAR reduce power consumption. The measurement results show that the proposed ADC achieved the SNDR of 68.32 dB, the SFDR of 79 dB, and the ENOB (effective number of bits) of 11.05 bits. The measured INL and DNL were 1.9LSB and 1.5LSB, respectively. The power consumption including all the digital circuits is 6.7 µW at the sampling frequency of 100 KHz under 3.3 V supply voltage and the FoM (figure of merit) is 49 fJ/conversion-step.

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“…Step control unit ignites the set signal to DAC control unit which sends a sample signal to the DAC in the second step (2). The MSB output of the DAC drives comparator.…”

Section: Asynchronous Controlmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A 12-b Asynchronous SAR Type ADC for Bio Signal Detection

Lim¹,

Kim²,

Yoon³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

show abstract

“…Power saving can be achieved in ADC through the selection of a suitable low-power ADC. The successive approximation ADC is known as one of the best candidates in terms of low-power [2]. This paper presents the design of a successive approximation ADC, and its modeling in the context of the conditioning circuit presented in [1].…”

Section: Introductionmentioning

confidence: 99%

Design and modeling of a successive approximation ADC for the electrostatic harvester of vibration energy

Khalil

Dudka

Galayko

et al. 2010

2010 IEEE International Behavioral Modeling and Simulation Workshop

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This paper presents a functional design and modeling of a successive approximation analog-to-digital converter (ADC) and its application in the conditioning circuit of the vibration energy harvester. The paper published on BMAS'09 highlighted the necessity of a smart digital control to calibrate the system, which requires in turn an ultra low power supplied ADC. The harvester and the ADC are designed using a CMOS 0.35µm High Voltage technology and modeled in a mixed VHDL-AMS/ELDO environment. The supply voltage of the ADC is 2.5V. The whole system was simulated using a mixed signal AdvanceMS simulator.

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CMOS Dual‐mode Energy‐harvesting‐image Sensor

2018

CMOS Integrated Lab‐on‐a‐Chip System for Personalized Biomedical Diagnosis

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An ultralow-energy adc for smart dust

Cited by 245 publications

References 11 publications

A 12-b Asynchronous SAR Type ADC for Bio Signal Detection

A 12-b Asynchronous SAR Type ADC for Bio Signal Detection

Design and modeling of a successive approximation ADC for the electrostatic harvester of vibration energy

CMOS Dual‐mode Energy‐harvesting‐image Sensor

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