An ultra-thin interposer utilizing 3D TSV technology

Chiou, W.C.; Yang, Kai-Shing; Yeh, J. H.; Wang, S.H.; Liou, Y.H.; Wu, Ting; Lin, Jiunn-Yuan; Huang, Chien-Yao; Lu, Shao-Wei; Hsieh, Cheng-Yu; Teng, Huaguo; Chiu, Catherine; Chang, Hun-Hsien; Wei, Ting-Hsun; Lin, Yu‐Cheng; Chen, Y.H.; Tu, Hongen; Ko, Han-Gon; Yu, Tianjun; Hung, Jaclyn Y.; Tsai, P.H.; Yeh, D.C.; Wu, Wen-Chin; Su, A.J.; Chiu, Steve; Hou, S. Y.; Shih, Da‐Yuan; Chen, Kim H.; Jeng, Shin-Puu; Yu, C. H.

doi:10.1109/vlsit.2012.6242484

Cited by 11 publications

(6 citation statements)

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“…Introduction A typical 2.5D interposer package consists of one or multiple guest dies stacked on top of a thinned TSV interposer, which is in turn assembled on either an organic flip chip BGA (FCBGA) or a ceramic substrate. [75][76][77][78][79] Figure 33 shows an example of a 2.5D interposer package. The two guest chips could be assembled side-by-side on the interposer as shown in the schematics or be replaced by one or more stacks of multiple dies (for example, memory cube).…”

Section: 5d Tsi Assembly Challengesmentioning

confidence: 99%

“…The CoW-first assembly flow integrates the TSV wafer processing with guest chip attach before completion of the TSI wafer fabrication and is known as chip-on-wafer-onsubstrate (CoWoS). [77][78][79] Section III B 3 describes the CoWoS process and an example of the assembled package. 1.…”

Section: B Tsi Package Assembly Process Flowmentioning

confidence: 99%

“…In this CoW-first assembly flow, [77][78][79] the guest dies are flip-chip bonded on TSI wafer after the completion of TSV formation, front-side multi-layer interconnect, and front-side micro-bump formation, but before back-side wafer thinning and TSV reveal during the TSI wafer fabrication. After the completion of guest chips attach, the CoW wafer is molded and thinned down to 100 lm or less from the backside to reveal the TSV and is followed by C4 bumping process before it is singulated into individual "CoW" dies for assembly onto substrate to complete the CoWoS process flow.…”

Section: Chip-on-wafer (Cow) First Assembly Flowmentioning

confidence: 99%

“…After the completion of guest chips attach, the CoW wafer is molded and thinned down to 100 lm or less from the backside to reveal the TSV and is followed by C4 bumping process before it is singulated into individual "CoW" dies for assembly onto substrate to complete the CoWoS process flow. This CoW-first assembly flow is heavily promoted by TSMC and is called CoWoS [77][78][79] technology. The schematics of the CoWoS process flow are shown in Figure 36.…”

Section: Chip-on-wafer (Cow) First Assembly Flowmentioning

confidence: 99%

See 3 more Smart Citations

Heterogeneous 2.5D integration on through silicon interposer

Zhang¹,

Lin²,

Wickramanayaka³

et al. 2015

Applied Physics Reviews

124

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Section: 5d Tsi Assembly Challengesmentioning

confidence: 99%

Section: B Tsi Package Assembly Process Flowmentioning

confidence: 99%

Section: Chip-on-wafer (Cow) First Assembly Flowmentioning

confidence: 99%

Section: Chip-on-wafer (Cow) First Assembly Flowmentioning

confidence: 99%

See 2 more Smart Citations

Heterogeneous 2.5D integration on through silicon interposer

Zhang¹,

Lin²,

Wickramanayaka³

et al. 2015

Applied Physics Reviews

124

View full text Add to dashboard Cite

“…Some key technologies needed to enable 3Di include the formation of through-silicon-vias (TSV), wafer bonding and wafer thinning. 3D integration can include a Si interposer, which is used to redirect circuitry between a chip carrier and one or more top chips [4,5]. High-precision alignment, positioning and bonding are required for the fabrication of various 3Di devices, especially for fine-pitch 3D.…”

Section: Introductionmentioning

confidence: 99%

Bonding technologies for chip level and wafer level 3D integration

Sakuma

Skordas

Zitz

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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This paper provides a comparison of bonding process technologies for chip and wafer level 3D integration (3Di). We discuss bonding methods and comparison of the reflow furnace, thermo-compression, Cavity ALignment Method (CALM) for chip level bonding, and oxide bonding for 300 mm wafer level 3Di. For chip 3Di, challenges related to maintaining thin die and laminate co-planarity were overcome. Stacking of large thin Si die with 22 nm CMOS devices was achieved. The size of the die was more than 600 mm 2 . Also, 300 mm 3Di wafer stacking with 45 nm CMOS devices was demonstrated. Wafers thinned to 10 µm with Cu through-silicon-via (TSV) interconnections were formed after bonding to another device wafer. In either chip or wafer level 3Di, testing results show no loss of integrity due to the bonding technologies.

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