An Ultra Low-Voltage RF Front-end Receiver for IoT Devices

Boosting RRAM-Based Mixed-Signal Accelerators in FD-SOI Technology for ML Applications

“…The circuit in Fig. 6(b) is the row-interface for input activations, including a PWM DAC [16] and an analog multiplexer, based on the NMOS M B3 and the transmission gate T G B1 , converting the output signal of the DAC from logic levels to the 0-V B range. SOI devices, with 1.8-V nominal voltage supply (and 2-V strength) and compliant with the programming procedure in Fig.…”

“…4(b). A PWM-DAC, based on a digital delay line, with a resolution in the 5-to-7-bit range, can be laid out on two rows of digital standard cells [16]. In 22-nm FD-SOI, this approximately corresponds to a vertical array pitch H c = 1.2 µm.…”

“…[20], [21], including only the consumption of the memory array and the interfaces, for a fair comparison. In our implementation, we consider the energy consumption of the DAC and of the ADC for mixed-signal accelerators, both in 22-nm, reported in [16] and [12]. An accelerator combining the F-2T2R cell with CMC type-2 is expected to achieve an energy efficiency, normalized to 1-b MAC, of 1260 1b-TOPS/W [22], at L r = 8, corresponding to 3.9-b weight resolution, and 7-b activations This value is approximately 10 times larger than the efficiency reported for the state-of-the art 1T1R accelerators [5], [7], [10].…”