An ultra-low-power voltage-mode asynchronous WTA-LTA circuit

Abstract

This paper presents an asynchronous mixed-signal WTA-LTA circuit conceived to carry out local minimummaximum indexing in massively parallel image processing arrays. The hardware is focused on energy-efficient operation. We describe a realization for the standard CMOS base process of a commercial 3-D TSV stack featuring a power consumption of only 20pW per elementary cell at 30fps. The proposed block is also capable of resolving small voltage differences without requiring any external reference. This leads to a hit percentage greater than 90% even when taking into account global process variations and mismatch conditions.

Winner-Take-All and Loser-Take-All Circuits: Architectures, Applications and Analytical Comparison

“…Large capacitors are needed for this circuit to reach higher resolutions, which affects its speed. A similar approach was applied in [35] for imaging. The capacitor is precharged in every pixel of the image sensor, as shown in Figure 15.…”

“…The time-domain WTA circuit illustrated in Figure 16a is presented in [47]. Here, the input signals control a reference clock A similar approach was applied in [35] for imaging. The capacitor is precharged in every pixel of the image sensor, as shown in Figure 15.…”

“…Non-unique winners may also occur when more than one output becomes High. A similar approach was applied in [35] for imaging. The capacitor is precharged in every pixel of the image sensor, as shown in Figure 15.…”