An ultra low noise readout integrated circuit for uncooled microbolometers

Abstract

A low noise readout architecture for uncooled microbolometer focal plane arrays is described. The on-chip readout circuit contains an integration circuit in which the bolometer current is directed injected into a capacitor, and exhibits extremely low noise with no decrease in signal by using an ultra low noise capacitive transimpedance amplifier (CTIA). The simple configuration of the integration circuit makes it possible to operate more circuits in parallel, and increases the integration time and number of pixels. A 40 9 30 uncooled microbolometer focal plane array based on the low noise ROIC was implemented on silicon using a 0.5 lm CMOS technology. The total output noise voltage is 260 lV RMS. A noise at this level is so low that can loosen required TCR in the bolometer material. Experimental values of voltage responsivities of 3.98 9 10 5 V/W on average at 1 Hz modulation frequency have been achieved.

A Modularized Noise Analysis Method with Its Application in Readout Circuit Design

“…where represents the time length of a frame and (3) can be comprehended as ( ) convolving a window function with int window length [15]. So in frequency domain the process can be expressed as where ( ) is the transfer function of photocurrent noise source to the " in " node and the contribution to the output noise of the integrator part is given in the form of power spectrum density (PSD) by…”

“…The photocurrent noise is related to the value of the generating photocurrent, which varies with the radiation intensity. Strictly speaking, it is pixel noise, which does not belong to the noise of readout circuits [15]. Thus the photocurrent noise will not be calculated in the paper.…”

Low-Power Low-Noise CTIA Readout Integrated Circuit Design for Thermal Imaging Applications

“…Other complex circuit techniques could be found in the literature [2]. Among these circuits, the CTIA ROIC is selected to perform the interface function; due to its high gain, low noise, stable detector bias control, good linearity and high injection efficiency [3][4][5][6][7][8][9][10][11]. The power consumption problem of the CTIA will be solved through the technique of the lowpower design.…”

“…The circuit techniques used for noise reduction are correlated double sampling (CDS) and chopper stabilization (CHS) [3][4][5][6][7][8][9][10][11][12][13]. The CDS is preferable in applications, which inherently use sampled-data circuits, so that the low-frequency noise behavior is not made worse by noise aliasing.…”

“…Basically, the DR is limited by the maximum integration voltage (V max ), the integration capacitor (C int ) and the readout noise of the circuit as shown in equation (1) [15] where, q is the electron charge. The DR can be widened either by changing the C int values [4][5][6][7][8][9][10][11][12][13][14][15][16], or by changing the integration time [9,12]. (1) This paper concerns with the application of a new widening DR technique to the CTIA ROIC based on the CDS circuit with emphasis on its power consumption and noise performance compared to other works.…”