An Ultra-Low Cost Multilayer RAM in Quantum-Dot Cellular Automata

Song, Zhixin; Xie, Guangjun; Cheng, Xin; Wang, Lei; Zhang, Yongqiang

doi:10.1109/tcsii.2020.2988046

Cited by 29 publications

(18 citation statements)

References 20 publications

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“…Song et al [7] have designed a novel loop-based RAM circuit using the developed 2-1 multiplexer and D-latch circuits. The half-cell misplacement method is utilized for the implementation of inverse operation in the developed multiplexer circuit.…”

Section: The Cam Circuitmentioning

confidence: 99%

“…The CMOS technology is a dominate technology for digital circuits design, but this technology has several concerns at nano-scale including short channel effects. The Quantumdot Cellular Automata (QCA) technology is a significant kind of nanotechnology for the implementation of digital circuits such as full adder, comparator, shift register, counter, multiplier, and memory [1][2][3][4][5][6][7][8]. This kind of nanotechnology has significantly low delay and area compared to CMOS technology [3,9].…”

Section: Introductionmentioning

confidence: 99%

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Efficient circuit design for content-addressable memory in quantum-dot cellular automata technology

2021

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Quantum-dot cellular automata (QCA) technology is a kind of nanotechnology utilized for building computational circuits. It can be a good technology for overcome CMOS drawbacks at nano-scale due to its low delay and area. The Content-Addressable Memory (CAM) is a very fast memory that can perform search operations in a very short time. This feature makes the relative popularity of these memories and many applications for them, especially in network routing and processors. In this study, a novel loop-based circuit is designed for the QCA memory unit, which reduces area, cell count, latency, and cost. The obtained results using QCADesigner tool version 2.0.3 demonstrate that the designed QCA memory unit utilizes 16 cells, 0.01 µm2 area, and 0.25 clock cycles and has a reduction of 33% in the number of cells, 50% in area, 50% in latency, and 75% in cost compared to existing works. Then, this memory unit is utilized to design an efficient structure for CAM circuit. The results show that the developed structure for CAM circuit has 0.75 clock cycles, 32 cells, and 0.03 µm2 area, and it has a reduction of 20% in the number of cells, 25% in area, 40% in latency, and 75% in cost compared to existing works.

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Section: The Cam Circuitmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Efficient circuit design for content-addressable memory in quantum-dot cellular automata technology

2021

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“…One of these nanotechnologies that is expected to provide the implementation of low-power, high-density, and high-speed integrated digital circuits is quantum-dot cellular automata (QCA) [7][8][9][10][11][12]. In the literature, many studies have been conducted on developing different QCA designs for various fundamental digital circuits such as Multiplexer (MUX) [13][14][15][16][17][18][19][20][21][22], XOR/XNOR [23], arithmetic circuits [24][25][26][27][28], memory [18], reversible gate [29], etc. If we investigate the development of QCA architectures, the designers used majority logic gates as a fundamental building block for the design of digital circuits.…”

Section: Introductionmentioning

confidence: 99%

“…An additional available QCA structure which is a modified majority gate reported in [32] was also used to develop a MUX [19]. Other designs were developed as special structures without considering the existing majority gate as a basic building block [13,17,18]. The current majority logic-based architectures limit the synthesis tools to constraint to a two-way design in which the first part is purely on functional level and then do a conversion of this functional level into a majority-based design.…”

Section: Introductionmentioning

confidence: 99%

Low-Power Multiplexer Structures Targeting Efficient QCA Nanotechnology Circuit Designs

2021

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Quantum-dot cellular automata (QCA) technology is considered to be a possible alternative for circuit implementation in terms of energy efficiency, integration density and switching frequency. Multiplexer (MUX) can be considered to be a suitable candidate for designing QCA circuits. In this paper, two different structures of energy-efficient 2×1 MUX designs are proposed. These MUXes outperform the best existing design in terms of power consumption with approximate reductions of 26% and 35%. Moreover, similar or better performance factors such as area and latency are achieved compared to the available designs. These MUX structures can be used as fundamental energy-efficient building blocks for replacing the majority-based structures in QCA. The scalability property of the proposed MUXes is excellent and can be used for energy-efficient complex QCA circuit designs.

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“…Such advantages led researchers to develop several projects detailing the construction of QCA circuits. In the recent years, several circuits such as address [3,4], sequential circuits [2,5], switching circuits [6,7], reversible logic circuit [8,9], and memories [10,11] have been designed. On the contrary, to cope with the challenge of IOT, big data domains and the need to achieve data rates of up to multiple gigabits per second require the use of more efficient routing algorithms to avoid network bottlenecks.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Nanotechnology QCA Geometric Greedy Router

Touil

Gassoumi

Mtibaa

2021

Journal of Electrical and Computer Engineering

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This paper presents an optimized geometric greedy router (GGR) based on quantum dot cellular automata (QCA) technology. The proposed structure of GGR is based on a spanning tree of the network. This type of communication does not require an IP address. It uses only local information and can be used in many communication devices. In this paper, we first describe the principal components of the router and then we present their QCA architecture. The QCA technology is the most likely alternative to replace conventional circuits (CMOS) due to their very low power consumption and high processing speed. To consider integration with other complex circuit, we have utilized QCA clock-phase-based technique for the proposed design architecture. The results obtained using the QCA designer tool exhibit the superiority of the presented architecture over the existing designs. The proposed structure shows a reduction of 30% reduction in occupied space. The power dissipation rate of the proposed design is analyzed by QCAPro tool to approve its reliability.

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An Ultra-Low Cost Multilayer RAM in Quantum-Dot Cellular Automata

Cited by 29 publications

References 20 publications

Efficient circuit design for content-addressable memory in quantum-dot cellular automata technology

Efficient circuit design for content-addressable memory in quantum-dot cellular automata technology

Low-Power Multiplexer Structures Targeting Efficient QCA Nanotechnology Circuit Designs

Design and Implementation of Nanotechnology QCA Geometric Greedy Router

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