An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power

Khaddam-Aljameh, Riduan; Francese, Pier Andrea; Benini, Luca; Eleftheriou, Evangelos

doi:10.1109/tvlsi.2020.3037871

Cited by 16 publications

(11 citation statements)

References 32 publications

(51 reference statements)

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“…to encode multi-bit data in a single physical quantity, such as time [7], [8], electrical current [9]- [12], charge [13]- [16],…”

Section: Ieee Journal Of Solid-state Circuitsmentioning

confidence: 99%

“…Each ADC measures the outputs of a multi-input-singleoutput (MISO) system, that is the result of a dot-product between a weight vector and an input vector. Therefore, the adjusted metrics of weight-and input-integral nonlinearity (INL)/differential nonlinearity (DNL) are adopted as proposed in [16]. The measured transfer curves that are shown in Fig.…”

Section: B Linearization Techniquementioning

confidence: 99%

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HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

Khaddam-Aljameh

Stanisavljević

Mas

et al. 2022

IEEE J. Solid-State Circuits

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We present a 256 × 256 in-memory compute (IMC) core designed and fabricated in 14-nm CMOS technology with backend-integrated multi-level phase change memory (PCM). It comprises 256 linearized current-controlled oscillator (CCO)-based A/D converters (ADCs) at a compact 4-µm pitch and a local digital processing unit (LDPU) performing affine scaling and ReLU operations. A frequency-linearization technique for CCO is introduced, which increases the maximum Manuscript

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“…to encode multi-bit data in a single physical quantity, such as time [7], [8], electrical current [9]- [12], charge [13]- [16],…”

Section: Ieee Journal Of Solid-state Circuitsmentioning

confidence: 99%

Section: B Linearization Techniquementioning

confidence: 99%

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

Khaddam-Aljameh

Stanisavljević

Mas

et al. 2022

IEEE J. Solid-State Circuits

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“…6(a), where T1-T6 constitute a 6T SRAM circuit, T7-T10 perform XNOR functions, and T11 and T12 decide the execution of the XNOR function. Su et al [43,62] proposed a two-way transpose multibit cell structure (Fig. 6(b)) that contains a common functional operation unit used by 16 6T cells to execute multiplication in the vertical or horizontal direction.…”

Section: Compact Coupling Structurementioning

confidence: 99%

“…The key to multibit multiplication is the weighting strategy. The weighting strategies include pulse width [10,35,36,39,40,45,50,56,64,66,71] , pulse height [10,15,16,44,56] , number of pulses [37,38] , width-to-length ratio of transistors [3,32,42,43,62] , capacitor array weighting [37,38,62,63,72,73] , and precharge time weighting [44] . The specific implementation strategy of the capacitor array weighting technology is introduced in Section 3.…”

Section: Multibit Multiplicationmentioning

confidence: 99%

A review on SRAM-based computing in-memory: Circuits, functions, and applications

Lin¹,

Tong²,

Zhang³

et al. 2022

J. Semicond.

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Artificial intelligence (AI) processes data-centric applications with minimal effort. However, it poses new challenges to system design in terms of computational speed and energy efficiency. The traditional von Neumann architecture cannot meet the requirements of heavily data-centric applications due to the separation of computation and storage. The emergence of computing in-memory (CIM) is significant in circumventing the von Neumann bottleneck. A commercialized memory architecture, static random-access memory (SRAM), is fast and robust, consumes less power, and is compatible with state-of-the-art technology. This study investigates the research progress of SRAM-based CIM technology in three levels: circuit, function, and application. It also outlines the problems, challenges, and prospects of SRAM-based CIM macros.

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“…Even without considering the speed mismatch between the memory and computing units, the power consumption generated by frequent data migration on the bus has far exceeded the calculation itself ( Gao and Kozyrakis, 2016 ; Horowitz, 2014 ; Verma et al., 2019 ). Under the influence of memory speed and power consumption, it is urgent to design a new architecture of the memory and computing units to achieve a breakthrough in the von Neumann bottleneck ( Agrawal et al., 2019 ; Khaddam-Aljameh et al., 2020 ; Kim et al., 2020 ; Liu et al., 2020 ).…”

Section: Introductionmentioning

confidence: 99%

Multifunctional computing-in-memory SRAM cells based on two-surface-channel MoS2 transistors

Wang

Zhang

et al. 2021

iScience

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Summary Driven by technologies such as machine learning, artificial intelligence, and internet of things, the energy efficiency and throughput limitations of the von Neumann architecture are becoming more and more serious. As a new type of computer architecture, computing-in-memory is an alternative approach to alleviate the von Neumann bottleneck. Here, we have demonstrated two kinds of computing-in-memory designs based on two-surface-channel MoS 2 transistors: symmetrical 4T2R Static Random-Access Memory (SRAM) cell and skewed 3T3R SRAM cell, where the symmetrical SRAM cell can realize in-memory XNOR / XOR computations and the skewed SRAM cell can achieve in-memory NAND / NOR computations. Furthermore, since both the memory and computing units are based on two-surface-channel transistors with high area efficiency, the two proposed computing-in-memory SRAM cells consume fewer transistors, suggesting a potential application in highly area-efficient and multifunctional computing chips.

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An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power

Cited by 16 publications

References 32 publications

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

A review on SRAM-based computing in-memory: Circuits, functions, and applications

Multifunctional computing-in-memory SRAM cells based on two-surface-channel MoS2 transistors

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An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power

Cited by 16 publications

References 32 publications

HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

A review on SRAM-based computing in-memory: Circuits, functions, and applications

Multifunctional computing-in-memory SRAM cells based on two-surface-channel MoS2 transistors

Contact Info

Product

Resources

About

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs