An SEU resistant 256 K SOI SRAM

Abstract

A novel SO1 memory cell has been implemented in a 1.0-pm 256K SRAM witha 20-ns worst-case minimum WRITE time at +125"C, and providing a single event upset (SEW immunity of less than 1 x lO-'O errors/bit-day over temperature. The worstcase supply voltage for SEU was found to be 5.5 V, rather than the usually assumed 4.5 V. This is attributed to bipolar effects of the SO1 transistor, and thus has possible implications for SEU testing of all SO1 memories.

SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments

“…7 therefore suggest that not only the gate regions of these SRAMs are sensitive, but also the reverse-biased drain regions. This is in contrast with conventional wisdom that only gate-region strikes cause upsets in SOI and SOS ICs [10], [19], [23], [24]. We have not performed full cross section simulations for the SOI SRAMs, but single-point Davinci simulations of n-channel gate and drain strikes are shown in Fig.…”

Basic mechanisms and modeling of single-event upset in digital microelectronics

“…Body ties are sometimes used commercially to reduce floating-body effects under dc operation, and careful attention to body tie design is crucial to maintaining good SEU performance [64], [95], [96]. Even in body-tied SOI designs, manufacturers have found it necessary to incorporate other hardening methods for applications where very high upset thresholds are desired [93], [97], [98]. Fully depleted SOI transistors exhibit reduced floating-body effects and in some (but not all) cases have shown excellent SEU performance [99].…”

“…For the most part, these techniques have not been widely used (if at all) and have their own associated tradeoffs. Capacitors have been successfully used as a feedback element in SOI SRAMs [65], [97], [98] and very recently as a means to improve the soft-error performance of deep-submicron CMOS SRAMs for terrestrial applications [107]. While adding capacitance still degrades timing parameters, one advantage is reduced temperature-dependence compared to resistive hardening.…”

3D Simulation of transient current and charge collection induced by heavy ion in SOI transistors

“…According to the experience that the gate region above body is the most sensitive regions of SOI device [3], [4], the devices are struck by ions at the middle of the device gate along the channel length direction, but each device's strike location is different along the channel width direction. The strike locations are 0.15μm, 0.3μm and 0.45μm away from the body contact, respectively.…”