An overview of through-silicon-via technology and manufacturing challenges

Gambino, J.; Adderly, Shawn A.; Knickerbocker, John

doi:10.1016/j.mee.2014.10.019

Cited by 213 publications

(110 citation statements)

References 162 publications

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“…[1][2][3][4][5] Meanwhile, the structure of devices becomes more complex migrating from 2D form to 3D architecture. 6 Consequently, the effective power density inside the devices increases enormously, which introduces a challenge for heat dissipation. Therefore, the reliability of devices would be vulnerable against thermal issue.…”

Section: Introductionmentioning

confidence: 99%

Defect induced phonon scattering for tuning the lattice thermal conductivity of SiO2 thin films

Cao

Zhu

2017

AIP Advances

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In this work, the thermal properties of nanoscale SiO2 thin films have been systematically investigated with respect to the thickness, crystal orientations and the void defects using non-equilibrium molecular-dynamics (NEMD) simulation. Size effect for the lattice thermal conductivity of nanoscale SiO2 thin films was observed. Additionally, SiO2 thin films with [001] oriented exhibited greater thermal conductivity compared with other crystal orientations which was discussed in terms of phonon density of states (PDOS). Furthermore, the porosity of void defects was introduced to quantify the influence of defects for thermal conductivity. Results exhibited that the thermal conductivity degraded with the increase of porosity. Two thermal conductivity suppression mechanisms, namely, void defects induced material loss interdicting heat conduction and phonon scattering enhanced by the boundary of defects, were proposed. Then, a further simulation was deployed to find that the effect of boundary scattering of defects was dominant in thermal conductivity degradation compared with material loss mechanism. The conclusion suggests that the thermal conductivity could be configured via regulating the distribution of PDOS directly associated with void defects.

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Section: Introductionmentioning

confidence: 99%

Defect induced phonon scattering for tuning the lattice thermal conductivity of SiO2 thin films

Cao

Zhu

2017

AIP Advances

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“…However, there are still some challenges for establishing the optimal process for copper filling because the influence of feature of TSV, complicated mechanisms of additives behaviors and complicated fabricated process. 2 A predictive numerical model of the copper electrodeposition process is a very helpful tool to investigate the optimal process with some advantages, such as low cost and efficiency. A typical numerical model should have the ability to predict feature evolution of copper electrodeposition under different operating conditions.…”

mentioning

confidence: 99%

RETRACTED: Copper Electrodeposition in Through-Silicon Via under Galvanostatic Condition

Luo

Chen

Zhang

et al. 2016

J. Electrochem. Soc.

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We present a tertiary current-distribution model for copper electrodeposition under galvanostatic conditions, with detailed surface chemistry kinetics for the model system of copper electrodeposition. The values of the kinetic parameters are extracted from results of statistical chronoamperometry and linear sweep voltammetry experiments using a potential-dependent, diffusion-adsorptiondesorption model of the experimental system. The resulting surface chemistry description is combined with fundamental conservation laws, including mass transport, potential distribution, and competitive adsorption, to form the tertiary current distribution model. Two-dimensional finite element simulations of this model provide information about the causes of the thickness of the copper electrodeposition layer, including potential variations of the cathodic surface, fluctuations in the cupric ion concentration and coverage of the accelerator. The model is used to predict the filling process with different current densities and SPS concentrations and is verified by copper electrodeposition experiments. The "optimal zone" was determined for the SPS concentration and the inward current density to achieve good TSV filling. Sample points in the outer zone were selected and the failure mechanism was studied to help to infer the right direction toward the "optimal zone" in copper electrodeposition. The models are potentially useful tools for measuring the properties of electrolyte solutions and for the optimization of copper electrodeposition processes. Through-Silicon via (TSV) is one of key techniques for 3D integration with many advantages. The electroplated copper is a major interconnect material in TSV due to its high electrical conductivity, lower cost than alternative deposition methods.1,2 Copper electrodeposition as an efficient method of metallization is widely accepted, and it has been proposed by many researchers. [3][4][5] According to the feature of TSV on chip, some special additives such as accelerator (Bis-(3-sulfopropyl) disulfide, or SPS), suppressor (Polyethylene glycol, or PEG), leveler (Janus Green B) and Cl − , are usually applied in electrolyte solution to assist copper filling with void-free.6-8 An appropriate distribution of additives provides a fast growth at the bottom and the growth rate at via opening is suppressed, as improper distribution of additives result in unfilled feature.9 Hence, behaviors of additives on the cathode surface are very important for TSV filling process. However, there are still some challenges for establishing the optimal process for copper filling because the influence of feature of TSV, complicated mechanisms of additives behaviors and complicated fabricated process.2 A predictive numerical model of the copper electrodeposition process is a very helpful tool to investigate the optimal process with some advantages, such as low cost and efficiency. A typical numerical model should have the ability to predict feature evolution of copper electrodeposition under different operating conditi...

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“…Such variations can be as large as 50% for p-MOSFETs [20] and thus require the definition of keep-away-zones around the TSVs with dimensions on the order of 10-20 µm [1], or even larger in the case of analog circuits where high precision matching of the device properties of the silicon transistors is required [21].…”

Section: Introductionmentioning

confidence: 99%

Through Silicon Vias With Invar Metal Conductor for High-Temperature Applications

Asiatici

Laakso

Fischer

et al. 2017

J. Microelectromech. Syst.

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Abstract-Through silicon vias (TSVs) are key enablers of 3D integration technologies which, by vertically stacking and interconnecting multiple chips, achieve higher performances, lower power and a smaller footprint. Copper is the most commonly used conductor to fill TSVs; however, copper has a high thermal expansion mismatch in relation to the silicon substrate. This mismatch results in a large accumulation of thermomechanical stress when TSVs are exposed to high temperatures and/or temperature cycles, potentially resulting in device failure.In this paper, we demonstrate 300 µm long, 7:1 aspect ratio TSVs with Invar as a conductive material. The entire TSV structure can withstand at least 100 thermal cycles from -50• C to 190• C and at least one hour at 365 • C, limited by the experimental setup. This is possible thanks to matching coefficients of thermal expansion (CTE) of the Invar via conductor and of silicon substrate. This results in thermomechanical stresses that are one order of magnitude smaller compared to copper TSV structures with identical geometries, according to finite element modelling. Our TSV structures are thus a promising approach enabling 2.5D and 3D integration platforms for high-temperature and harsh-environment applications.

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An overview of through-silicon-via technology and manufacturing challenges

Cited by 213 publications

References 162 publications

Defect induced phonon scattering for tuning the lattice thermal conductivity of SiO2 thin films

Defect induced phonon scattering for tuning the lattice thermal conductivity of SiO2 thin films

RETRACTED: Copper Electrodeposition in Through-Silicon Via under Galvanostatic Condition

Through Silicon Vias With Invar Metal Conductor for High-Temperature Applications

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