An overview of the modeling and simulation of the single event transients at the circuit level

Andjelković, Marko; Ilić, Aleksandar; Stamenković, Zoran; Krstić, Miloš; Kraemer, Rolf

doi:10.1109/miel.2017.8190065

Cited by 24 publications

(14 citation statements)

References 33 publications

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“…The circuits with the nanoscale become sensitive to the environment radiation and ionizing energy particles such as neutrons and alpha particles 33 . This effect is called the single event effect (SEE) 34 and gives an overview of the existing SEE models. The types of SEE are single event transient (SET) induced in combinational circuits and SEU induced in memories and flip‐flops.…”

Section: Stability and Reliabilitymentioning

confidence: 99%

Ternary SRAM circuit designs with CNTFETs

Abdelrahman

Fouda

Alouani

et al. 2023

Circuit Theory & Apps

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Summary Static random‐access memory (SRAM) is a cornerstone in modern microprocessors architecture, as it has high power consumption, large area, and high complexity. Also, the stability of the data in the SRAM against the noise and the performance under the radian exposure are main concern issues. To overcome these limitations in the quest for higher information density by memory element, the ternary logic system has been investigated, showing promising potential compared with the conventional binary base. Moreover, carbon nanotube field effect transistor (CNTFET) is a new alternative device with proper features like low power consumption and threshold voltage dependency on diameter. This paper proposes a new design for ternary SRAM using CNTFET and its evaluation by comparing it against two other designs in many aspects. Moreover, we investigated the static noise margin for the three designs to discuss their stability. Furthermore, we studied the reliability of the designs by evaluating the soft errors effect.

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Section: Stability and Reliabilitymentioning

confidence: 99%

Ternary SRAM circuit designs with CNTFETs

Abdelrahman

Fouda

Alouani

et al. 2023

Circuit Theory & Apps

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“…For the simulation =200ps, =50ps and =50µA. This model simulates the effects of a high-energy particle strike on a sensitive node, helping us gauge potential outcomes [20]. The Q c in SRAM memory is in uenced by various factors, including memory size, device scaling, and operating voltage.…”

Section: Single Event Upset and Analysismentioning

confidence: 99%

Design a Hybrid Memory Array for Radiation-Hardened SRAM in Satellite Image Compression Systems

Sharma,

Neema

2023

Preprint

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In the satellite technology landscape, the satellite industry is crucial across military, meteorology, safety, climate monitoring, and landscape mapping sectors. The demand for high-quality satellite imagery has led to innovations in image processing and compression techniques to overcome challenges such as data storage limitations and slow upload speeds. This paper focuses on optimizing on-board SRAM memory cells for satellite image compression, addressing issues like radiation-induced errors, memory size, and power efficiency. A hybrid memory array is proposed, allocating reliable cells for Most Significant Bits (MSB) and less reliable cells for Least Significant Bits (LSB), optimizing area, power, and data integrity. The research evaluates SRAM cell sensitivity to radiation-induced Single Event Upsets (SEUs), with simulation results indicating smaller cell sizes and lower operating voltages increase susceptibility. Simulate a comparative analysis involving radiation-hardened SRAM cells, including CC18T, RHC14T, RHMC12T, SARP12T, SRRD12T, and PCELL10T, and proposed 12T. Proposed 12T cell is significantly 1.22x/3.77x/3.9x/4.1x/1.86x less write delay then CC18T/RHC14T/RHMC12T/SRRD12T/PCELL10T, respectively. Additionally, 2.27x/1.98x/71.29x lower read access time than RHMC12T/SARP12T/SRRD12T memory cells. The area occupied by our proposed cell is substantially smaller, with it being 2.03x/1.39x/1.18x/1.6x/1.09x less than CC18T/RHC14T/RHMC12T/ SRRD12T / PCELL10T. Furthermore, observed improvements in read, write and hold Noise Margins, and critical charge. Introduced an Electrical Quality Metric (EQM) to provide a comprehensive assessment of SRAM cell performance, and our proposed cell excels in terms of EQM compared to the others.

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“…However, its replication can be complex since the methodology does not depend only on device-level simulations. If the reader is interested in a more in-depth review of the modeling of SET, the authors refer the reader to the works of Pasupathy et al [10] and Andjelkovic et al [11].…”

Section: B Set Electrical Modelingmentioning

confidence: 99%

Single Event Transient on Combinational Logic: An Introduction and their Mitigation

Kessler

Ferraz

Rosa

et al. 2022

JICS

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Single event transients pose a major threat to the reliability of modern VLSI designs. Improving the robustness of combinational logic is challenging due to its complexity, masking effects, and signal dependence. This paper presents the mechanisms and concepts of SET generation, modeling, masking, and propagation in combinational logic. It also discusses design parameters and their impact on circuit robustness. An overview of automated design strategies for radiation hardening by design and their advantages and disadvantages is provided, covering gate sizing, gate duplication, gate remapping, load increase, layout spacing, and charge sharing techniques.

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An overview of the modeling and simulation of the single event transients at the circuit level

Cited by 24 publications

References 33 publications

Ternary SRAM circuit designs with CNTFETs

Ternary SRAM circuit designs with CNTFETs

Design a Hybrid Memory Array for Radiation-Hardened SRAM in Satellite Image Compression Systems

Single Event Transient on Combinational Logic: An Introduction and their Mitigation

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