An Optimized Systolic Array Architecture for Full-Search Block Matching Algorithm and its-Implementation on FPGA chips

Mohammadzadeh, Mohammad; Eshghi, Mohammad; Azadfar, M.M.

doi:10.1109/newcas.2005.1496700

Cited by 13 publications

(9 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…QSDS-DIC FPGA results were compared to FS [2], FTS (Flexible Triangle Search) [3] and FS+PS4:1 and early termination architectures [4], as presented in Table IV. Solutions [2] and [3] have a constant throughput and [4] have a variable throughput due to the early termination.…”

Section: Synthesis Resultsmentioning

confidence: 99%

“…Solutions [2] and [3] have a constant throughput and [4] have a variable throughput due to the early termination. The search area used by [4] is 32x32 samples, while [2] and [3] do not present this information. Table IV shows the synthesis results comparisons of [2], [3], [4] and QSDS-DIC architecture.…”

Section: Synthesis Resultsmentioning

confidence: 99%

“…The search area used by [4] is 32x32 samples, while [2] and [3] do not present this information. Table IV shows the synthesis results comparisons of [2], [3], [4] and QSDS-DIC architecture. The processing rate of HDTV frames (1920x1080) is also presented.…”

Section: Synthesis Resultsmentioning

confidence: 99%

See 2 more Smart Citations

Architectural design for the new QSDS with dynamic iteration control motion estimation algorithm targeting HDTV

Porto

Bampi

Susin

et al. 2008

Proceedings of the 21st Annual Symposium on Integrated Circuits and System Design

View full text Add to dashboard Cite

This paper presents a high throughput and low hardware cost architecture for motion estimation (ME) using a Quarter Subsampled Diamond Search algorithm (QSDS) with Dynamic Iteration Control (DIC). QSDS-DIC is a new algorithm proposed in this paper, which was developed to focus an efficient hardware design of ME. QSDS-DIC is based on the well known Diamond Search algorithm (DS) and on the sub-sampling technique. Besides this, DIC was developed to allow better synchronization and quality. A software evaluation presents the average results for quality and computational cost of QSDS, QSDS-DIC, Full Search and DS block matching algorithms. The designed hardware architecture considered blocks with 16x16 samples. The architecture was described in VHDL and mapped to a Xilinx Virtex-4 FPGA and to TSMC 0.18µm CMOS standard cells. Synthesis results for FPGA indicate that QSDS-DIC architecture is able to run at 213.3 MHz, while taking only 3610 LUTs. This architecture can reach real time for HDTV (1920x1080 pixels) in the worst case, and it can process 188 HDTV frames per second in the average case.

show abstract

Section: Synthesis Resultsmentioning

confidence: 99%

Section: Synthesis Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Architectural design for the new QSDS with dynamic iteration control motion estimation algorithm targeting HDTV

Porto

Bampi

Susin

et al. 2008

Proceedings of the 21st Annual Symposium on Integrated Circuits and System Design

View full text Add to dashboard Cite

show abstract

“…Hardware implementation of these algorithms [11][12][13][14][15][16][17] aims at achieving the fastest computation with optimal number of hardware gates, which affects hardware cost and power consumption, by using hardware pipelining and parallelism techniques.…”

Section: Introductionmentioning

confidence: 99%

Efficient search area loading technique for block-based motion estimation and its FPGA implementation using flexible triangle search algorithm

Rehan

Nashed

2009

2009 International Conference on Computer Engineering &Amp; Systems

View full text Add to dashboard Cite

An efficient technique for loading search area in block-based motion estimation is proposed. The main advantage of the proposed technique is to reduce number of search area loading cycles by taking advantage of the vertical and horizontal overlap between adjacent search areas and thus improve the overall performance of the motion search and frame encoding. The proposed technique was implemented in FPGA as part of the flexible triangle search (FTS) motion estimation algorithm. However, the proposed technique can be used in similar search algorithm. The FTS is a fast block-matching algorithm for motion estimation proposed in previous work. The FTS can be used for block-based motion estimation where it can locate the best matching blocks between two frames using a search triangle that changes its direction and its size through a set of operations. These operations provide the triangle with the large flexibility to locate the best matching block in less number of search iterations. Simulation results indicates that the proposed technique reduces number of cycles required for motion estimation by around 8% and thus enable the video encoder to support higher frequencies or larger resolutions. The proposed design was implemented, simulated, and tested using VHDL and synthesized using Xilinx ISE for the Xilinx Spartan3 device. The results obtained were compared to an FPGA implementation of the FTS algorithm published in previous work.

show abstract

“…Of previously reported FPGA implementations [9][10][11][12][13][14][15][16], only two [15,16] support VBS-ME, and both are bit-parallel. A most significant bit (MSB)-first bit-serial design with early termination was proposed for QCIF resolution video [13] which employed a FS within the range −15 to +16.…”

Section: Introductionmentioning

confidence: 99%

Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors

Leong

2007

J Sign Process Syst Sign Image

View full text Add to dashboard Cite

H.264/AVC is the latest video coding standard adopting variable block size motion estimation (VBS-ME), quarter-pixel accuracy, motion vector prediction and multi-reference frames for motion estimation. These new features result in much higher computation requirements than previous coding standards. In this paper we propose a novel most significant bit (MSB) first bit-serial architecture for full-search block matching VBS-ME, and compare it with systolic implementations. Since the nature of MSB-first processing enables early termination of the sum of absolute difference (SAD) calculation, the average hardware performance can be enhanced. Five different designs, one and two dimensional systolic and tree implementations along with bitserial, are compared in terms of performance, pixel memory bandwidth, occupied area and power consumption.

show abstract

An Optimized Systolic Array Architecture for Full-Search Block Matching Algorithm and its-Implementation on FPGA chips

Cited by 13 publications

References 8 publications

Architectural design for the new QSDS with dynamic iteration control motion estimation algorithm targeting HDTV

Architectural design for the new QSDS with dynamic iteration control motion estimation algorithm targeting HDTV

Efficient search area loading technique for block-based motion estimation and its FPGA implementation using flexible triangle search algorithm

Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors

Contact Info

Product

Resources

About