An Optimized Selective Harmonic Minimization-PWM Scheme for Cascaded H-Bridge Inverter Fulfilling NRS 048-2:2003 Grid code

Improved SHM‐PAM‐based five‐level CHB inverter to fulfil NRS 048‐2:2003 grid code and to apply as shunt active power filter with tuned proportional‐resonant controller for improving power quality

“…Hence, harmonic mitigation [24][25][26][27][28][29][30][31] and harmonic minimisation [32,33] techniques have been introduced that mitigate or minimise some certain number of lower order harmonics below the permissible limits mentioned by the grid code standards. Harmonic mitigation technique was first introduced by Franquelo et al in [24] for a three-level neutral-point-clamped (NPC) inverter using 15 number of switching that meets CIGRE WG 36-05 and EN50160.…”

“…This study introduces an improved SHM‐PAM technique for three‐phase five‐level CHB inverter where least number of switching (four numbers) based quarter‐wave symmetric waveform pattern using equally variable DC‐link voltages has been adopted to fulfil the NRS 048‐2:2003 (first time introduced by the authors) grid code standard. A preliminary investigation of the proposed SHM‐PAM technique has been carried out in [32]. In this study, a considerable amount of work both in simulation and experiment has been carried out further, and the additional contributions are highlighted as follows: In this work, the proposed SHM‐PAM and conventional SHE‐PWM techniques have been implemented on a laboratory scale experimental setup of 3‐ph 5‐level CHB inverter.…”