An Operational Amplifier Assisted Input Buffer and An Improved Bootstrapped Switch for High-Speed and High-Resolution ADCs

Cao, Yuefeng; Zhang, Tianli; Chen, Yongzhen; Ye, Fan; Ren, Junyan

doi:10.1109/iscas.2018.8351071

Cited by 14 publications

(4 citation statements)

References 9 publications

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“…Some of them e.g. Bootstrapped switch (Nazzal and Mahmoud, 2016), charge-pump technique (Al-daloo et al , 2016); amplifier assisted input buffer (Cao et al , 2018), spate control mechanism circuit (Ramkaj et al , 2018), dummy switch (Zheng et al , 2017), tracking amplifier (Du et al , 2017), driver circuit (Razavi, 2014) and pull-down switch (Chan et al , 2016) are currently being used.…”

Section: Literature Workmentioning

confidence: 99%

Energy and time-efficient circuitry of bat-bootstrap and comp-lifier for ultra-low power SAR-ADC

Faheem

Zhong

Azeem

et al. 2021

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Purpose Successive Approximation Register-Analog to Digital Converter (SAR-ADC) has been achieved notable technological advancement since the past couple of decades. However, it’s not accurate in terms of size, energy, and time consumption. Many projects proposed to make it energy efficient and time-efficient. Such designs are unable to deliver two parallel outputs. Design/methodology/approach To this end, this study introduced an ultra-low-power circuitry for the two blocks (bootstrap and comparator) of 11-bit SAR-ADC. The bootstrap has three sub-parts: back-bone, left-wing and right-wing, named as bat-bootstrap. The comparator block has a circuitry of the two comparators and an amplifier, named as comp-lifier. In a bat-bootstrap, the authors plant two capacitors in the back-bone block to avoid the patristic capacitance. The switching system of the proposed design highly synchronized with the short pulses of the clocks for high accuracy. This study simulates the proposed circuits using a built-in Cadence 90 nm Complementary Metal Oxide Semiconductor library. Findings The results suggested that the response time of two bat-bootstrap wings and comp-lifier are 80 ns, 120 ns, and 90 ns, respectively. The supply voltage is 0.7 V, wherever the power consumption of bat-bootstrap, comp-lifier and SAR-ADC are 0.3561µW, 0.257µW and 35.76µW, respectively. Signal to Noise and Distortion Ratio is 65 dB with 5 MHz frequency and 25 KS/s sampling rate. The input referred noise of the amplifier and two comparators are 98µVrms, 224µVrms and 224µVrms, respectively. Originality/value Two basic circuit blocks for SAR-ADC are introduced, which fulfill the duality approach and delivered two outputs with highly synchronized clock pulses. The circuit sharing concept introduced for the high performance SAR-ADCs.

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Section: Literature Workmentioning

confidence: 99%

Energy and time-efficient circuitry of bat-bootstrap and comp-lifier for ultra-low power SAR-ADC

Faheem

Zhong

Azeem

et al. 2021

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“…Thus, they are made up by several larger capacitors in series. In addition, bootstrapped switches [24,25] are utilized at the input of the modulator to improve the linearity of sampled signals. The clock timing waveform is given in Fig.…”

Section: Circuit Realization Of the σ-δ Modulatormentioning

confidence: 99%

A 3rd-order 1-bit Σ-Δ modulator with a 2-tap FIR filter embedded

Chen

Wang

2019

IEICE Electron. Express

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This paper presents a low-voltage 3 rd -order single-bit switchedcapacitor Σ-Δ modulator implemented in a 40-nm CMOS technology. In the modulator, a 2-tap FIR (finite impulse response) filter is employed in the feedback loop to reduce the integrator output swings. With the help of digital assisted techniques, the number of the sampling capacitors in the first integrator is reduced to mitigate the performance deterioration caused by capacitor mismatch. Besides, the inverter-based amplifiers with dynamic-biased structure are proposed to reduce the power consumption. The proposed modulator is sampled at 25.6 MHz over a bandwidth of 100 kHz. The modulator achieves a max SNR (signalto-noise ratio) of 92.1 dB, a max SNDR (signal-to-noise and distortion ratio) of 87.3 dB, and a DR (dynamic range) of 88.1 dB under the supply voltage of ²0.45 V while consuming a total power consumption of 790 µW.

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“…Bootstrap designed in Cao et al (2018) is primarily for highresolution ADCs. An amplifier was used to obtain high linearity.…”

Section: Introductionmentioning

confidence: 99%

Bio-inspired circuitry of bee-bootstrap and Spider-latch comparator for ultra-low power SAR-ADC

Faheem

Zhong

Wang

et al. 2021

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Purpose There are many types of the ADCs implemented in the mobile and wireless devices. Most of these devices are battery operated and operational at low input voltage. SAR ADC is popular for its low power operations and simple architecture. Scientists are still working to make its working faster under the same low power area. There are many SAR-ADC implemented in the past two decades, but still, there is a big room for dual SAR-ADC. Design/methodology/approach The authors are presenting a dual SAR-ADC with a smaller number of components and blocks. The proposed ultra-low-power circuit of the SAR-ADC consists of four major blocks, which include Bee-bootstrap, Spider-Latch dual comparator, dual SAR-logic and dual digital to analog converter. The authors have used the 90-nm CMOS library for the construction of the design. Findings The power breaks down of the comparator are dramatically improved from 0.006 to 0.003 uW. The ultimate design has 5 MHz operating frequency with 25 KS/s sampling frequency. The supply voltage is 1.2 V with 35.724 uW power consumption. Signal-to-noise and distortion ratio and spurious-free dynamic range are 65 and 84 dB, respectively. The Walden's figure of merits calculated 7.08 fj/step. Originality/value The authors are proposing two-in-one circuit for SAR-ADC named as “dual SAR-ADC”, which obeys the basic equation of duality, derived and proved under the heading of proposed solution. It shows a clear difference between the performance of two circuit-based ADC and one dual circuit ADC. The number of components is reduced by sharing the work load of some key components.

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An Operational Amplifier Assisted Input Buffer and An Improved Bootstrapped Switch for High-Speed and High-Resolution ADCs

Cited by 14 publications

References 9 publications

Energy and time-efficient circuitry of bat-bootstrap and comp-lifier for ultra-low power SAR-ADC

Energy and time-efficient circuitry of bat-bootstrap and comp-lifier for ultra-low power SAR-ADC

A 3rd-order 1-bit Σ-Δ modulator with a 2-tap FIR filter embedded

Bio-inspired circuitry of bee-bootstrap and Spider-latch comparator for ultra-low power SAR-ADC

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