A 3rd-order 1-bit Σ-Δ modulator with a 2-tap FIR filter embedded

Abstract

This paper presents a low-voltage 3 rd -order single-bit switchedcapacitor Σ-Δ modulator implemented in a 40-nm CMOS technology. In the modulator, a 2-tap FIR (finite impulse response) filter is employed in the feedback loop to reduce the integrator output swings. With the help of digital assisted techniques, the number of the sampling capacitors in the first integrator is reduced to mitigate the performance deterioration caused by capacitor mismatch. Besides, the inverter-based amplifiers with dynamic-biased structure are proposed to reduce the power consumption. The proposed modulator is sampled at 25.6 MHz over a bandwidth of 100 kHz. The modulator achieves a max SNR (signalto-noise ratio) of 92.1 dB, a max SNDR (signal-to-noise and distortion ratio) of 87.3 dB, and a DR (dynamic range) of 88.1 dB under the supply voltage of ²0.45 V while consuming a total power consumption of 790 µW.

A 0.4-V 6.6-<i>µ</i>W 75-dB SNDR delta-sigma modulator employing gate-body-driven amplifier with local CMFB loop and robust clock generator for implantable biomedical devices

“…Therefore it is more difficult to design high signal-to-noise and distortion (SNDR) DSM by passive integrator compared with active integrator. Although inverter-based OTAs are developed to implement low-power DT DSMs [22,23,24,25,26]. They are more vulnerable to VDD variation and circuit parasitics [27].…”