An open platform for developing multiprocessor SoCs

Nava, Mario Diaz; Blouet, Patrick; Teninge, P.; Coppola, Marcello; Ben-Ismail, T.; Picchiottino, S.; Wilson, Robin

doi:10.1109/mc.2005.218

Cited by 17 publications

(8 citation statements)

References 3 publications

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“…They can be used to validate intellectual property blocks, but are not flexible enough for fast MPSoC design exploration or detailed statistics extraction. In the academic world, a recent emulation platform for exploring performance of MPSoC alternatives is TC4SOC [25]. It uses a proprietary 32-bit VLIW core and enables exploration of interconnects by using an FPGA, but, it does not enable detailed extraction of statistics and performing thermal modeling at the other three architectural levels proposed in this work, i.e., memory hierarchy, interconnects and processing cores.…”

Section: Related Workmentioning

confidence: 99%

Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling

Valle

Atienza

2011

Microelectronics Journal

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Abstract-New tendencies envisage 2D/3D Multi-Processor System-On-Chip (MPSoC) as a promising solution for the consumer electronics market. MPSoCs are complex to design, as they must execute multiple applications (games, video), while meeting additional design constraints (energy consumption, time-to-market, etc.). Moreover, the rise of temperature in the die for MPSoCs, especially for forthcoming 3D chips, can seriously affect their final performance and reliability. In this context, transient thermal modeling is a key challenge to study the accelerated thermal problems of MPSoC designs, as well as to validate the benefits of active cooling techniques (e.g., liquid cooling), combined with other state-of-the-art methods (e.g., dynamic frequency and voltage scaling), as a solution to overcome run-time thermal runaway.In this paper, I present a novel approach for fast transient thermal modeling and analysis of 2D/3D MPSoCs with active cooling, which relies on the exploitation of combined hardwaresoftware emulation and linear thermal models for liquid flow. The proposed framework uses FPGA emulation as the key element to model the hardware components of 2D/3D MPSoC platforms at multi-megahertz speeds, while running real-life software multimedia applications. This framework automatically extracts detailed system statistics that are used as input to a scalable software thermal library, using different ordinary differential equation solvers, running in a host computer. This library calculates at run-time the temperature of on-chip components, based on the collected statistics from the emulated system and the final floorplan of the 2D/3D MPSoC. This approach creates a close-loop thermal emulation system that allows MPSoC designers to validate different hardware-and software-based thermal management approaches, including liquid cooling injection control, under transient and dynamic thermal maps. The experimental results with 2D/3D MPSoCs illustrate speed-ups of more than three orders of magnitude compared to cycle-accurate MPSoC thermal simulators, at the same time as preserving the accuracy of the estimated temperature within 3% of traditional approaches using finite-element simulations for 3D stacks and liquid cooling.

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Section: Related Workmentioning

confidence: 99%

Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling

Valle

Atienza

2011

Microelectronics Journal

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“…They can be used to validate IPs, but are not flexible enough for fast MPSoC design exploration or detailed statistics extraction. In the academic world, the most complete emulation platform up-to-date for exploring MPSoC alternatives is TC4SOC [7]. It uses a propietary 32-bit VLIW core and enables the exploration of the interconnection mechanisms and different protocols by using an FPGA to reconfigure the network interfaces.…”

Section: Related Workmentioning

confidence: 99%

A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework

Valle

Atienza

Magan

et al. 2006

2006 IFIP International Conference on Very Large Scale Integration

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Abstract-With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor System-On-Chip (MPSoC) architectures have become widespread. These new systems are very complex to design as they must execute multiple complex real-time applications (e.g. video processing, or videogames), while meeting several additional design constraints (e.g. energy consumption or time-to-market). Therefore, mechanisms to efficiently explore the different possible HW-SW design interactions in complete MPSoC systems are in great need. In this paper, we present a new FPGA-based emulation framework that allows designers to rapidly explore a large range of MPSoC design alternatives at the cycle-accurate level. Our results show that the proposed framework is able to extract a number of critical statistics from processing cores, memory and interconnection systems, with a speed-up of three orders of magnitude compared to cycleaccurate MPSoC simulators.

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“…Systems running on reconfigurable and reprogrammable architectures can be adapted to new standards and system updates. Currently, there are a couple of approaches for novel reconfigurable and reprogrammable architectures in the focus of research [4]. An architecture composed of a programmable architecture block like an application specific instruction set processor (ASIP) or a general purpose processor (GPP) and reconfigurable embedded field programmable gate array (eFPGA) seems to be a promising platform [1] [14] [18].…”

Section: Introductionmentioning

confidence: 99%

Modelling and Quantitative Analysis of Coupling Mechanisms of Programmable Processor Cores and Arithmetic Oriented eFPGA Macros

Sydow

Korb

Neumann

et al. 2006

2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006)

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Advances in semiconductor technology and ever growing complexity of modern digital systems facilitate the design of novel architectures integrating former self-contained architecture blocks on one die. In this contribution a SoC basically combined of a RISC processor core and an arithmetic oriented eFPGA is modelled, quantitatively analysed and in particular coupling aspects of the eFPGA and the RISC processor core are discussed. These coupling mechanisms are quantitatively evaluated in terms of energy efficiency, area and performance. Furthermore, decisive design parameters for the coupling like the degree of coupling etc. are discussed and compared with other realisations for exemplary operators (DES, median filter).

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An open platform for developing multiprocessor SoCs

Cited by 17 publications

References 3 publications

Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling

Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling

A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework

Modelling and Quantitative Analysis of Coupling Mechanisms of Programmable Processor Cores and Arithmetic Oriented eFPGA Macros

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