An Online EHW Pattern Recognition System Applied to Face Image Recognition

Glette, Kyrre; Tørresen, Jim; Yasunaga, Masahiro

doi:10.1007/978-3-540-71805-5_30

Cited by 21 publications

(36 citation statements)

References 11 publications

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“…The FUR approach has also been shown to handle a larger number of categories in [10]. In contrast, the experiment presented in this paper used only of few input features and a rather moderate number of categories.…”

Section: Discussionmentioning

confidence: 99%

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A Comparison of Evolvable Hardware Architectures for Classification Tasks

Glette

Tørresen

Kaufmann

et al. 2008

Evolvable Systems: From Biology to Hardware

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Abstract. We analyze and compare four different evolvable hardware approaches for classification tasks: An approach based on a programmable logic array architecture, an approach based on two-phase incremental evolution, a generic logic architecture with automatic definition of building blocks, and a specialized coarse-grained architecture with pre-defined building blocks. We base the comparison on a common data set and report on classification accuracy and training effort. The results show that classification accuracy can be increased by using modular, specialized classifier architectures. Furthermore, function level evolution, either with predefined functions derived from domain-specific knowledge or with functions that are automatically defined during evolution, also gives higher accuracy. Incremental and function level evolution reduce the search space and thus shortens the training effort.

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Section: Discussionmentioning

confidence: 99%

“…An online EHW architecture for classification tasks was proposed in [10,11]. The architecture was applied to multiple-category face image recognition and sonar return classification.…”

Section: Related Workmentioning

confidence: 99%

A Comparison of Evolvable Hardware Architectures for Classification Tasks

Glette

Tørresen

Kaufmann

et al. 2008

Evolvable Systems: From Biology to Hardware

Self Cite

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“…The Functional Unit Row (FUR) architecture for classification tasks was first presented by Glette in [12]. It is an architecture tailored to online evolution combined with fast reconfiguration.…”

Section: The Reconfigurable Functional Unit Row Architecturementioning

confidence: 99%

“…In the following, we present the organization of the FUR architecture, the principle of the reconfigurable FUR architecture, and the applied evolutionary technique. For details about the implementation of FUR we refer to [12]. matching primitives [9,10].…”

Section: The Reconfigurable Functional Unit Row Architecturementioning

confidence: 99%

“…The novelty is that we investigate classifier systems able to cope with changing resources at runtime and evaluate their classification performance while changing the size of the utilized chip area. To this end, we leverage the Functional Unit Row (FUR) architecture, a scalable and run-time reconfigurable classifier architecture introduced by Glette et al [12]. During optimization, we increase and decrease the number of pattern matching elements included in FUR and study the development of the resulting classification accuracy and, specifically, the recovery capability of FUR.…”

Section: Introductionmentioning

confidence: 99%

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Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture

Knieper

Kaufmann

Glette

et al. 2010

Evolvable Systems: From Biology to Hardware

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Abstract. The evolvable hardware paradigm facilitates the construction of autonomous systems that can adapt to environmental changes and degrading effects in the computational resources. Extending these scenarios, we study the capability of evolvable hardware classifiers to adapt to intentional run-time fluctuations in the available resources, i.e., chip area, in this work. To that end, we leverage the Functional Unit Row (FUR) architecture, a coarse-grained reconfigurable classifier, and apply it to two medical benchmarks, the Pima and Thyroid data sets from the UCI Machine Learning Repository. We show that FUR's classification performance remains high during changes of the utilized chip area and that performance drops are quickly compensated for. Additionally, we demonstrate that FUR's recovery capability benefits from extra resources.

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