An on Chip Network inside a FPGA for Run-Time Reconfigurable Low Latency Grid Communication

Strunk, Jochen; Volkmer, Toni; Rehm, Wolfgang; Schick, H.

doi:10.1109/dsd.2009.133

“…The Erlangen Slot Machine [50,51] is an example of an architecture using crossbar or crossbar-like communication architectures; the system includes an external programmable crossbar, and can also use an on-chip crossbar-like Figure 2.6: Multiplexer-Based Fully Connected Crossbar architecture [97] which implements multiple parallel buses connected through switches, each of which can connect two functional units directly. A fully connected network architecture is presented in [98]; the architecture allows processing elements to connect directly to all other processing elements via multiple communication channels in a non-blocking fashion, achieving the same link pattern as a fully-connected crossbar.…”

Section: Fully-connected Crossbarmentioning

confidence: 99%

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

Dumitriu¹

2023

Preprint

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A number of modern digital processing systems implement complex multi-mode applications with high performance requirements and strict operating constraints; examples include video processing and telecommunication applications. A number of these systems use increasingly large FPGAs as the implementation medium, due to reduced development costs. The combination of increases in FPGA capacity and system complexity has lead to a non-linear increase in system implementation effort. If left unchecked, implementation effort for such systems will reach the point where it becomes a design and development bottleneck. At the same time, the reduction in transistor size used to manufacture these devices can lead to increased device fault rates. To address these two problems, the Multi-mode Adaptive Collaborative Reconfigurable self-Organized System (MACROS) Framework and design methodology is proposed and described in this work. The MACROS Framework other the ability for run-time architecture adaptation by integrating FPGA configuration into regular operation. The MACROS Framework allows for run-time generation of Application-Specific Processors (ASPs) through the deployment, assembly and integration of pre-built functional units; the framework further allows the relocation of functional units without affecting system functionality. The use of functional units as building blocks allows the system to be implemented on a piece-by-piece basis, which reduces the complexity of mapping, placement and routing tasks; the ability to relocate functional units allows fault mitigation by avoiding faulty regions in a device. The proposed framework has been used to implement multiple video processing systems which were used as verification and testing instruments. The MACROS framework was found to successfully support run-time architecture adaptation in the form of functional unit deployment and relocation in high performance systems. For large systems (more than 100 functional units), the MACROS Framework implementation effort, measured as time cost, was found to be one third that of a traditional (monolithic) system; more importantly, in MACRO Systems this time cost was found to increase linearly with system complexity (the number of functional units). When considering fault mitigation capabilities, the resource overhead associated with the MACROS Framework was found to be up to 85 % smaller than a traditional Triple Module Redundancy (TMR) solution.

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“…The Erlangen Slot Machine [50,51] is an example of an architecture using crossbar or crossbar-like communication architectures; the system includes an external programmable crossbar, and can also use an on-chip crossbar-like Figure 2.6: Multiplexer-Based Fully Connected Crossbar architecture [97] which implements multiple parallel buses connected through switches, each of which can connect two functional units directly. A fully connected network architecture is presented in [98]; the architecture allows processing elements to connect directly to all other processing elements via multiple communication channels in a non-blocking fashion, achieving the same link pattern as a fully-connected crossbar.…”

Section: Fully-connected Crossbarmentioning

confidence: 99%

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

Dumitriu¹

2023

Preprint

0

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A number of modern digital processing systems implement complex multi-mode applications with high performance requirements and strict operating constraints; examples include video processing and telecommunication applications. A number of these systems use increasingly large FPGAs as the implementation medium, due to reduced development costs. The combination of increases in FPGA capacity and system complexity has lead to a non-linear increase in system implementation effort. If left unchecked, implementation effort for such systems will reach the point where it becomes a design and development bottleneck. At the same time, the reduction in transistor size used to manufacture these devices can lead to increased device fault rates. To address these two problems, the Multi-mode Adaptive Collaborative Reconfigurable self-Organized System (MACROS) Framework and design methodology is proposed and described in this work. The MACROS Framework other the ability for run-time architecture adaptation by integrating FPGA configuration into regular operation. The MACROS Framework allows for run-time generation of Application-Specific Processors (ASPs) through the deployment, assembly and integration of pre-built functional units; the framework further allows the relocation of functional units without affecting system functionality. The use of functional units as building blocks allows the system to be implemented on a piece-by-piece basis, which reduces the complexity of mapping, placement and routing tasks; the ability to relocate functional units allows fault mitigation by avoiding faulty regions in a device. The proposed framework has been used to implement multiple video processing systems which were used as verification and testing instruments. The MACROS framework was found to successfully support run-time architecture adaptation in the form of functional unit deployment and relocation in high performance systems. For large systems (more than 100 functional units), the MACROS Framework implementation effort, measured as time cost, was found to be one third that of a traditional (monolithic) system; more importantly, in MACRO Systems this time cost was found to increase linearly with system complexity (the number of functional units). When considering fault mitigation capabilities, the resource overhead associated with the MACROS Framework was found to be up to 85 % smaller than a traditional Triple Module Redundancy (TMR) solution.

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Survey of Dynamically Reconfigurable Network-on-Chip

Gu

¹

2011

2011 International Conference on Future Computer Sciences and Application

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An on Chip Network inside a FPGA for Run-Time Reconfigurable Low Latency Grid Communication

Cited by 3 publications

References 10 publications

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

Survey of Dynamically Reconfigurable Network-on-Chip

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