An on-chip glitchy-clock generator for testing fault injection attacks

Endo, S.; Sugawara, Takeshi; Homma, Naofumi; Aoki, Takafumi; Satoh, Akashi

doi:10.1007/s13389-011-0022-y

Cited by 65 publications

(40 citation statements)

References 11 publications

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“…Numbers of possible hardware attacks are described in [7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25]. Based on the implementation methods, we have categorized this all methods in three different categories of hardware attack on crypto-hardware system as shown in fig.2 The main focus of attacker is to retrieve secret key from crypto-hardware as mentioned in literature even though traditionally having multiple goals in mind.…”

Section: Implementation Attacks On Crypto-hardwarementioning

confidence: 99%

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2016

VLSICS

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Section: Implementation Attacks On Crypto-hardwarementioning

confidence: 99%

“…smartcard). Clock glitches can be invoked by hardware equipment called low end FPGA board [16], [14]. …”

Section: Clock Glitchesmentioning

confidence: 99%

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2016

VLSICS

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“…The CDBs have four stages in this design. An on-chip glitchy-clock generator [15] and its related circuit are implemented in another FPGA on the same board in order to examine the actual delay time (i.e., FS) of the AES module (t AES ) in an automatic manner. Figure 11 shows the image of the glitchy clock signal produced by the glitchy-clock generator.…”

Section: B Evaluation Of An Fpga Implementationmentioning

confidence: 99%

An Efficient Countermeasure against Fault Sensitivity Analysis Using Configurable Delay Blocks

Endo

Homma

et al. 2012

2012 Workshop on Fault Diagnosis and Tolerance in Cryptography

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In this paper, we present an efficient countermeasure against Fault Sensitivity Analysis (FSA) based on a configurable delay blocks (CDBs). FSA is a new type of fault attack which exploits the relationship between fault sensitivity and secret information. Previous studies reported that it could break cryptographic modules equipped with conventional countermeasures against Differential Fault Analysis (DFA) such as redundancy calculation, Masked AND-OR and Wave Dynamic Differential Logic (WDDL). The proposed countermeasure can detect both DFA and FSA attacks based on setup time violation faults. The proposed ideas are to use a CDB as a time base for detection and to combine the technique with Li's countermeasure concept which removes the dependency between fault sensitivities and secret data. Post-manufacture configuration of the delay blocks allows minimization of the overhead in operating frequency which comes from manufacture variability. In this paper, we present an implementation of the proposed countermeasure, and describe its configuration method. We also investigate the hardware overhead of the proposed countermeasure implemented in ASIC for an AES module and demonstrate its validity through an experiment using a prototype FPGA implementation.

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“…Endo et.al. [6] presented an on-chip clock-glitch generator with the accuracy of 0.17ns. Although the design of the generator is ingenious, it's not precise enough for our fault injection attacks.…”

Section: Introductionmentioning

confidence: 99%

Clock Glitch Fault Injection Attacks on an FPGA AES Implementation

2017

JEEEM

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Abstract. The Advanced Encryption Standard (AES) algorithm has been widely used to secure communication systems. However, the encryption algorithm is vulnerable to fault injection attacks and various attack methods have been studied. Some methods are just proposed in theory and have not been validated in practice. In this paper, we actualize a fault injection attack on an FPGA AES implementation. We propose a method to generate the highly accurate clock glitch to inject faults in the encryption process. We show that if the frequency of the clock glitch is carefully selected, only 6 faulty ciphertexts are necessary to discover the secret key.

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An on-chip glitchy-clock generator for testing fault injection attacks

Cited by 65 publications

References 11 publications

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An Efficient Countermeasure against Fault Sensitivity Analysis Using Configurable Delay Blocks

Clock Glitch Fault Injection Attacks on an FPGA AES Implementation

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