An Efficient Countermeasure against Fault Sensitivity Analysis Using Configurable Delay Blocks

Abstract

In this paper, we present an efficient countermeasure against Fault Sensitivity Analysis (FSA) based on a configurable delay blocks (CDBs). FSA is a new type of fault attack which exploits the relationship between fault sensitivity and secret information. Previous studies reported that it could break cryptographic modules equipped with conventional countermeasures against Differential Fault Analysis (DFA) such as redundancy calculation, Masked AND-OR and Wave Dynamic Differential Logic (WDDL). The proposed countermeasure can detect both DFA and FSA attacks based on setup time violation faults. The proposed ideas are to use a CDB as a time base for detection and to combine the technique with Li's countermeasure concept which removes the dependency between fault sensitivities and secret data. Post-manufacture configuration of the delay blocks allows minimization of the overhead in operating frequency which comes from manufacture variability. In this paper, we present an implementation of the proposed countermeasure, and describe its configuration method. We also investigate the hardware overhead of the proposed countermeasure implemented in ASIC for an AES module and demonstrate its validity through an experiment using a prototype FPGA implementation.

Fundamental Study on a Mechanism of Faulty Outputs from Cryptographic Modules Due to IEMI

“…Therefore, in the case that the electromagnetic waves injected from outside act as glitches, disturb the normal clock timing, and form faults as the abovementioned mechanism, it is possible to implementing circuit‐level countermeasures to ensure performing processing only at the normal clock timing and suppress the faulty output as well as reduce the risk of the secret key being analyzed.…”

Glitch-Resistant Masking Schemes as Countermeasure Against Fault Sensitivity Analysis

“…By only allowing the results of the combinational logic to the inputs of the capturing register after its outputs have been stabilized using an enable signal, the fault sensitivity is made constant and equal to the arrival of the enable signal. This method was shown possible by Endo et al by choosing the enable signal to be greater than the largest critical path delay of the circuit during postmanufacturing reconfiguration [30], [31].…”

Advanced fault analysis techniques on AES

“…The authors of [7], [3] discussed several ways to remove the dependency between the secret information and the FS information as an countermeasure against the FSA attack.…”