An NMOS buffer amplifier

Rodriguez, B.A.; Temes, Gábor C.; Martin, K.; Law, S.; Handy, R.; Kadekodi, N.

doi:10.1109/t-ed.1984.21502

Cited by 3 publications

(2 citation statements)

References 2 publications

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“…A common-gate (CG) transistor with a large transconductance g m can be used at the expense of either a large device or a large amount of current. Shunt feedback can be used to increase the effective g m , as is done in regulated cascode buffers (RGC) [6]. The limited voltage gain from a common source (CS) stage implies lower loop-gain, and thus, a limited Z in reduction.…”

Section: Front End Interface Electronicsmentioning

confidence: 99%

A CMOS front-end interface ASIC for SiPM-based positron emission tomography imaging systems

Dey

Rudell

Lewellen

et al. 2017

2017 IEEE Biomedical Circuits and Systems Conference (BioCAS)

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A current-mode interface chip for Silicon Photomultiplier (SiPM) array based positron emission tomography (PET) imaging front-ends is described. The circuit uses a high-speed current amplifier with a low input impedance, to minimize signal loss at the SiPM amplifier interface. To reduce the impact of dark noise, a novel high-speed threshold detection/comparator circuit is used to remove unwanted noise events. A prototype chip interfaces an array of SiPMs to the digital backend of a Positron Emission Tomography (PET) system using 64 readout channels, each of which contain a current amplifier and a threshold detection component. To reduce the number of backend channels, a row-column pulse positioning architecture (RCA) has been implemented. The ASIC occupies an area of 14.04 mm2 in 130nm STMicroelectronics HCMOS9GP process. The measured input impedance of the current amplifier is 20 ohms at 10 MHz, while the threshold detection circuit’s propagation delay is 0.3-2ns.

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Section: Front End Interface Electronicsmentioning

confidence: 99%

A CMOS front-end interface ASIC for SiPM-based positron emission tomography imaging systems

Dey

Rudell

Lewellen

et al. 2017

2017 IEEE Biomedical Circuits and Systems Conference (BioCAS)

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“…A common-gate TIA can provide a low input resistance at the cost of larger power consumption and input-referred noise [12][13]. To alleviate these challenges, a regulated-cascode (RGC) [14] TIA is introduced to lower the input resistance by increasing the effective transconductance, however it increases the power consumption [12][13]. The shunt-feedback TIA with a common-source amplifier can be an alternative thanks to providing an inductive impedance at the input in addition to lowering the input resistance [12][13], however it shows a trade-off between the transimpedance gain and power consumption.…”

Section: Introductionmentioning

confidence: 99%

An Inductorless Optical Receiver Front-End Employing a High Gain-BW Product Differential Transimpedance Amplifier in 16-nm FinFET Process

Kashani

Shakiba

Sheikholeslami

2023

IEEE Open J. Circuits Syst.

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In this paper, a fully-differential transimpedance amplifier (TIA) providing a high gain-BW product (GBP) is introduced. In the proposed architecture, a cascode cross-coupled structure is employed to double the effective transconductance of the cascode devices, improving the BW of the TIA. Moreover, a differential architecture is implemented using an RC highpass filter along with a buffer stage requiring smaller capacitance and resistance. Furthermore, a single-ended negative capacitance generation (NCG) circuit is employed at the input of the TIA to partially compensate for the input parasitic capacitances. A TIA including the proposed techniques, designed and laid out in a 16-nm FinFET process, demonstrates 57% and 79% better figure-of-merit compared to cascode and conventional TIAs designed along with the proposed TIA for a fair comparison, respectively. Post-layout simulations in companion with statistical analysis are employed to verify the effectiveness of the proposed architecture. From simulation results, the optical receiver achieves a peak transimpedance gain of 58.5 dBΩ, a BW of 14.8 GHz, an input-referred noise of 33.6 pA/√Hz, and an eye-opening of 30 mV at a data-rate of 56 Gbps PAM4 and at a bit-error-rate (BER) of 1E-6. The whole circuit consume 49 mW and occupies an active area of 0.0076 mm 2 .

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A 0.5-ms 47.5-nJ Resistor-to-Digital Converter for Resistive BTEX Sensor Achieving 0.1-to-5 ppb Resolution

Lee

Cho

Lee

et al. 2023

IEEE J. Solid-State Circuits

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An NMOS buffer amplifier

Cited by 3 publications

References 2 publications

A CMOS front-end interface ASIC for SiPM-based positron emission tomography imaging systems

A CMOS front-end interface ASIC for SiPM-based positron emission tomography imaging systems

An Inductorless Optical Receiver Front-End Employing a High Gain-BW Product Differential Transimpedance Amplifier in 16-nm FinFET Process

A 0.5-ms 47.5-nJ Resistor-to-Digital Converter for Resistive BTEX Sensor Achieving 0.1-to-5 ppb Resolution

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