An MRAM-Based Deep In-Memory Architecture for Deep Neural Networks

Patil, Ameya; Hua, Haocheng; Gonugondla, Sujan K.; Kang, Mingu; Shanbhag, Naresh R.

doi:10.1109/iscas.2019.8702206

Cited by 40 publications

(8 citation statements)

References 28 publications

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“…However, the majority of the inputs/outputs are moved across MAC arrays and from global buffers. Table 2 [49][50][51][52][53][54][55][56][57][58][59][60][61] reviews parts of recently emerged embedded NVM-based MAC operations. Most of the publications were applied to inference applications and depend on ADC-DAC blocks for signal conversion.…”

Section: Architecture-level Explorationmentioning

confidence: 99%

A survey of in-spin transfer torque MRAM computing

Cai

Liu

Chen

et al. 2021

Sci. China Inf. Sci.

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In traditional von Neumann computing architectures, the essential transfer of data between the processor and memory hierarchies limits the computational efficiency of next-generation system-on-a-chip. The emerging in-memory computing (IMC) approach addresses this issue and facilitates the movement of significant data and rapid computations. Among the different memory types, intrinsic energy efficiency is demonstrated by in-magnetic random access memory (MRAM) computing with a low-power spintronic magnetic tunnel junction device and hybrid integration at an advanced complementary metal-oxide semiconductor node. This study reviews state-of-the-art techniques for managing IMC with an emphasis on spin-transfer torque-MRAM computing via design schemes at the bit-cell, circuit, and system levels. In addition, this study presents effective design techniques and potential challenges and demonstrates the existing limitations of in-MRAM computing and potential methods for overcoming these issues. This study also considers the design technology co-optimization from the IMC perspective.

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Section: Architecture-level Explorationmentioning

confidence: 99%

A survey of in-spin transfer torque MRAM computing

Cai

Liu

Chen

et al. 2021

Sci. China Inf. Sci.

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“…MRAM cannot be directly used for analog IMC due to limited TMR. [37] proposes a new analog computing structure with operational amplifier integrator circuit, which uses the difference of the current flowing through R P and R AP to complete the calculation. This method alleviates the problem of limited TMR, but it has a high requirement on the performance of operational amplifier.…”

Section: Digital and Analog Realization Of Imcmentioning

confidence: 99%

Proposal of Analog In-Memory Computing with Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell

Cai¹,

Guo²,

Liu³

et al. 2021

Preprint

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In-memory computing (IMC) is an effectual solution for energy-efficient artificial intelligence applications. Analog IMC amortizes the power consumption of multiple sensing amplifiers with analog-to-digital converter (ADC), and simultaneously completes the calculation of multi-line data with high parallelism degree. Based on a universal one-transistor one-magnetic tunnel junction (MTJ) spin transfer torque magnetic RAM (STT-MRAM) cell, this paper demonstrates a novel tunneling magnetoresistance (TMR) ratio magnifying method to realize analog IMC. Previous concerns include low TMR ratio and analog calculation nonlinearity are addressed using device-circuit interaction. Peripheral circuits are minimally modified to enable in-memory matrix-vector multiplication. A current mirror with feedback structure is implemented to enhance analog computing linearity and calculation accuracy. The proposed design maximumly supports 1024 2-bit input and 1-bit weight multiply-andaccumulate (MAC) computations simultaneously. The 2-bit input is represented by the width of the input (IN) pulses, while the 1-bit weight is stored in STT-MRAM and the ×7500 magnified TMR (m-TMR) ratio is obtained by latching. The proposal is simulated using 28-nm CMOS process and MTJ compact model. The integral nonlinearity is reduced by 57.6% compared with the conventional structure. 9.47-25.4 TOPS/W is realized with 2-bit input, 1-bit weight and 4-bit output convolution neural network (CNN).

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“…In the last decade, important advances in nanotechnology have provided neuromorphic researchers with a panoply of new devices which allow for ultra low-power synaptic plasticity. Programmable resistors that have been proposed and tested as synapses include memristors [Jo et al, 2010], resistive random-access memory , phase-change memory [Ambrogio et al, 2016], ferroelectric field-effect transistors [Jerry et al, 2017], flash memory [Guo et al, 2017], magnetic random-access memory [Patil et al, 2019], conductive-bridging random access memory [Cha et al, 2020] and spin-transfer-torque memory [Vincent et al, 2015], among others. We refer to Burr et al [2017] for a review on the use of programmable resistors for neuromorphic computing.…”

Section: Programmable Resistors As Synapsesmentioning

confidence: 99%

Training End-to-End Analog Neural Networks with Equilibrium Propagation

Kendall,

Pantone,

Manickavasagam

et al. 2020

Preprint

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We introduce a principled method to train end-to-end analog neural networks by stochastic gradient descent. In these analog neural networks, the weights to be adjusted are implemented by the conductances of programmable resistive devices such as memristors [Chua, 1971], and the nonlinear transfer functions (or 'activation functions') are implemented by nonlinear components such as diodes. We show mathematically that a class of analog neural networks (called nonlinear resistive networks) are energy-based models: they possess an energy function as a consequence of Kirchhoff's laws governing electrical circuits. This property enables us to train them using the Equilibrium Propagation framework [Scellier and Bengio, 2017]. Our update rule for each conductance, which is local and relies solely on the voltage drop across the corresponding resistor, is shown to compute the gradient of the loss function. Our numerical simulations, which use the SPICEbased Spectre simulation framework to simulate the dynamics of electrical circuits, demonstrate training on the MNIST classification task, performing comparably or better than equivalent-size software-based neural networks. Our work can guide the development of a new generation of ultra-fast, compact and low-power neural networks supporting on-chip learning. * Currently at Google. Preprint. Under review.

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An MRAM-Based Deep In-Memory Architecture for Deep Neural Networks

Cited by 40 publications

References 28 publications

A survey of in-spin transfer torque MRAM computing

A survey of in-spin transfer torque MRAM computing

Proposal of Analog In-Memory Computing with Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell

Training End-to-End Analog Neural Networks with Equilibrium Propagation

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