An LSI digital signal processor

Thompson, John; Boddie, J.

doi:10.1109/icassp.1980.1171062

Cited by 14 publications

(3 citation statements)

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“…The quality offered by this system is perceptually equivalent to that of 16 kbits/s SB.C, which was judged in an earlier experiment [24] to -be perceptually equivalent to 24 kbits/s ACPCM. An efficient implementation of this system could be based on the recently announced digital processing (DSP) chip by Bell Laboratories [25], [26]. Moreover, the SBC/HS system could also be attractive at 16 kbits/s since its quality is only somewhat lower than ATC at this rate but is sufficiently less complex.…”

Section: Discussionmentioning

confidence: 99%

Performance of transform and subband coding systems combined with harmonic scaling of speech

Malah

Crochiere²,

Cox³

1981

IEEE Trans. Acoust., Speech, Signal Process.

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In this study an approach for improving the performance of waveform coders, based on coding a frequency scaled speech signal, is examined and subjectively evaluated for specific subband and transform coding systems. The recently developed simple and efficient timedomain harmonic scaling (TDHS) algorithms are used to frequency scale the speech signal. The underlying frequency.domain model of the pitch-adaptive TDHS algorithms provides insight and guidelines for their use in this application, as outlined in this work. The subjective evaluation is based on an A-B comparison test involving 12 listeners and shows a meaningful improvement in quality for the waveform coders used at low bit rates. In particular, subband coding (SBC) combined with TDHS (SBC/HS) at 9.6 kbits/s was found to provide a quality equivalent to that of SBC alone at 16 kbits/s, i.e., a bit-rate advantage of about 7 kbits/s was realized. For the speech specific adaptive transform coder (ATC) used, the combined system (ATC/HS) achieves a bit-rate advantage of 4 kbits/s at 7.2 kbits/s. The SBC/HS system emerges as a particuinrly attractive method for speech encoding at the data rate of 9.6 kbits/s since its quality is comparable to that of ATC/HS (or SBC at 16 kbits/s). Yet, its complexity is lower than ATC and the system is amenable to real-time hardware implementation using current technology. I. INTRODUCTION W AVEFORM coding techniques attempt to reproduce encoded signals at lower bit rates than PCM encoding by utilizing the temporal and spectral properties of the signal. Speech-specific coders have achieved sizeable reductions in bit rate by incorporating in the coder design known properties of both short-time and long-time (pitch period) correlations which are related to spectral envelope (forniants) arid fine structure (pitch harmonics) of speech, respectively. However, because they attempt to replicate the speech waveform, even the more complex forms of waveform coders, such as adaptive-predictive coders (APC) [1], [2] and adaptive transform coders (ATC) [3], [4], require bit rates typically at or above 9.6 kbits/s in order to have acceptable communication quality [5]. This range of bit rates is several times higher than the bit-rate range of vocoders which typically encode speech at 2.4 kbits/s and below [5]. Vocoders are based on a speech production model and achieve low bit rates by analyzing and Manuscript

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Section: Discussionmentioning

confidence: 99%

Performance of transform and subband coding systems combined with harmonic scaling of speech

Malah

Crochiere²,

Cox³

1981

IEEE Trans. Acoust., Speech, Signal Process.

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“…は 1980 年に登場したベル研究所の DSP-20(1) ，(2) と NEC のμ PD7720(3) ， (4) が最初である．ただし，ベル研西谷隆夫正員：フェロー首都大学東京システムデザイン学部 Takao NISHITANI, Fellow(The Department of System Design, Tokyo Metropolitan University, Hino-shi, 191-0065 Japan). Fundamentals Review Vol.1 No.4 pp.…”

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The Advent of DSP and Its Growth in Human Society

Nishitani

2008

IEICE Fundamentals Review

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“…Each set hardware can process 28 independent signals with 20 bit data word length at 4.48 MHz clock rate.…”

Section: A Digital Filters Applicationsmentioning

confidence: 99%

An LSI chip set for DSP hardware implementation

Kanemasa

Maruta²,

Nakayama³

et al.

ICASSP '81. IEEE International Conference on Acoustics, Speech, and Signal Processing

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This paper describes a new LSI chip set developed to provide a simple and cost-effective means for DSP hardware implementation. This chip set, consisting of two NMOS LSIs, contains enough logic and memOry to perform such high level DSP functions as biquad lilters and FFT buttef lies at a high throughput rate, without any other external logic devices. It employs serial arithmetic and operates at a clock rate up to mote than 5 MHz, Throughput rate can be traded-off with processing accuracy. Architecture is designed to pursue self-sufficient applicability to high level DSP functions, while retaining generalit' in application.

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An LSI digital signal processor

Cited by 14 publications

References 0 publications

Performance of transform and subband coding systems combined with harmonic scaling of speech

Performance of transform and subband coding systems combined with harmonic scaling of speech

The Advent of DSP and Its Growth in Human Society

An LSI chip set for DSP hardware implementation

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