An LSI chip set for DSP hardware implementation

Kanemasa, A.; Maruta, R.; Nakayama, Kenji; Sakamura, Y.; Tanaka, Shigenobu

doi:10.1109/icassp.1981.1171244

Cited by 11 publications

(5 citation statements)

References 6 publications

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“…Although a radix 2 dela commutator chip has been developed by NEC (ref 7), it is limited to clock rates of 5 MHz whic results in data rates of 10 MHz. In contrast, th radix 4 delay commutator operates at twice th clock rate and processes 4 data stream simultaneously to achieve a four fold increase i the data rates.…”

Section: The Delay Commutator Circuitmentioning

confidence: 99%

High Speed FFT Processor Implementation

Swartzlander

Stroll

1984

MILCOM 1984 - IEEE Military Communications Conference

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This paper describes recent progress in the implementation of a high speed Fast Fourier Transform (FFT) processor with state-of-the-art VLSI circuits. Initial efforts have produced FFT and inverse FFT processors that operate at data rates of up to 40 MHz (complex). The current implementation computes transforms of up to 16,384 points in length by means of the McClellan and Purdy radix 4 pipeline FFT algorithm.The arithmetic is performed by single chip 22 bit floating point adders and multipliers, while the interstage reordering is performed by delay commutators implemented with semi-custom VLSI. This paper explains the pipeline FFT implementation and focuses attention on our current activity which involves developing a fixed point arithmetic version using CMOS multipliers and adders to reduce the power consumption.

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Section: The Delay Commutator Circuitmentioning

confidence: 99%

High Speed FFT Processor Implementation

Swartzlander

Stroll

1984

MILCOM 1984 - IEEE Military Communications Conference

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“…Both transmultiplexers havebeen built using a "highlevel DSP chip set" that has been newly developed [22] to reduce size, cost, and power consumption for digital transmultiplexers, so that they can be competitive with conventional analog counterparts.…”

Section: R Maruta and A Kanemasa Are With The Communication Researchmentioning

confidence: 99%

“…Thus, a set of general purpose, high-density DSP building block elements, called a "high-level DSP chip set," has been developed [22]. The chip set consists of two LSI chips, the "arithmetic processor unit ( M U ) " and the "variable delay unit (mu)."…”

Section: Dsp Chip Set Developmentmentioning

confidence: 99%

24- and 120-Channel Transmultiplexers Built with New Digital Signal Processing LSI's

Maruta

Kanemasa

Sakaguchi³

et al. 1982

IEEE Trans. Commun.

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Abstracr-Two new digital transmultiplexers intended for commercial use have been developed. One transmultiplexer performs a bilateral conversion between two 12-channel FDM'group signals and a 24-channel PCM carrier signal. The other mutually connects two 60channel FDM sllpergroup signals and five 24-channel or four 30channel PCM signals. Both exploit a block processing digital SSB-FDM multiplex/demultiplex scheme employing a cascade of an FFT processor and a set of complex coefficient digital fhters. They have been built using newly developed high-level DSP LSI chips. Algorithmic considerations, developed LSI architecture, and equipment configuration ape described as well as digital processor design details and measured performance.

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“…Overall configuration of the PSK group demodulator z S(mTb) = x X(nTs) c(mTb -~T s ) ,(9) n = -x (m, n = 1 , 2 , 3 , . .…”

mentioning

confidence: 99%

A PSK group modem based on digital signal processing: Algorithm, hardware design, implementation and performance

Takahata

Yasunaga

Hirata

et al. 1988

Int. J. Satell. Commun.

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A PSK group modem which modulates and demodulates multiple PSK signals en bloc will play an important role in cost-effective satellite communications systems based on the narrow-band multicarrier PSWFDMA technique. This paper describes the development of a PSK group modem, including its algorithm, hardware design and implementation. In the algorithm, PSK signals are efficiently filtered by digital signal processing applied to the digital transmultiplexer. Furthermore, in order to compensate for the difference between the operation timing of the PSK group modem and the symbol timing of each inputloutput data signal, digital signal processing based on a table-look-up method using ROM and a rate-conversion filter with adaptive weighting are proposed for the modulator and demodulator, respectively. An experimental four-phase PSK group modem has been developed, and experiments have been conducted under various conditions. The measured performance of the developed hardware is also demonstrated.

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An LSI chip set for DSP hardware implementation

Cited by 11 publications

References 6 publications

High Speed FFT Processor Implementation

High Speed FFT Processor Implementation

24- and 120-Channel Transmultiplexers Built with New Digital Signal Processing LSI's

A PSK group modem based on digital signal processing: Algorithm, hardware design, implementation and performance

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