An Investigation of Linearity Performance and Intermodulation Distortion of GME CGT MOSFET for RFIC Design

Ghosh, Prahlad C.; Haldar, Subhasis; Gupta, R. S.; Gupta, Mridula

doi:10.1109/ted.2012.2219537

Cited by 154 publications

(94 citation statements)

References 20 publications

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“…2b that transconductance of GEWE-SiNW is higher in comparison to conventional SiNW MOSFET due to enhanced on-current. Also, significant enhancement in g m of our device is obtained as compared to previously reported work [27].…”

Section: Simulation Methodology and Calibrationsupporting

confidence: 74%

Impact of device parameter variation on RF performance of gate electrode workfunction engineered (GEWE)-silicon nanowire (SiNW) MOSFET

2015

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In this paper, we explore the quantitative investigation of the high-frequency performance of gate electrode workfunction engineered (GEWE) silicon nanowire (SiNW) MOSFET and compared with silicon nanowire MOSFET(SiNW MOSFET) using device simulators: ATLAS and DEVEDIT 3D. Simulation results demonstrate the improved RF performance exhibited by GEWE-SiNW MOS-FET over SiNW MOSFET in terms of transconductance (g m ), cut-off frequency ( f T ), maximum oscillator frequency ( f MAX ), power gains (Gma, G MT ) parasitic capacitances, stern's stability factor and intrinsic delay. Further, using three-dimensional device simulations, we have also examined the efficacy of parameter variations in terms of oxide thickness, radius of silicon nanowire, channel length and gate metal workfunction engineering on RF/microwave figure of merits of GEWE-SiNW MOSFET. Simulation result reveals significant enhancement in f T and f MAX ; and a reduction in switching time in GEWE-SiNW MOSFET due to alleviated short channel effects, improved drain current and smaller parasitic capacitance, thus providing detailed knowledge about the device's RF performance at such aggressively scaled dimensions.

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Section: Simulation Methodology and Calibrationsupporting

confidence: 74%

Impact of device parameter variation on RF performance of gate electrode workfunction engineered (GEWE)-silicon nanowire (SiNW) MOSFET

2015

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“…In this respect, in order to investigate linearity, 1‐dB compression point is considered as one of the key performance matrices. According to , it is given by

1 - d B compression point = 0.22 \sqrt{\frac{g_{m 1}}{g_{m 3}}}

where

g_{m 1} = \frac{\partial I_{d s}}{\partial V_{g s}}

g_{m 3} = \frac{\partial^{3} I_{d s}}{\partial V_{g s}^{3}} .

…”

Section: Linearity Analysismentioning

confidence: 99%

“…In this respect, in order to investigate linearity, 1-dB compression point is considered as one of the key performance matrices. According to [18][19][20][21][22], it is given by…”

Section: Linearity Analysismentioning

confidence: 99%

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Effect of gate‐length downscaling on the analog/RF and linearity performance of InAs‐based nanowire tunnel FET

Baral¹,

Biswal²,

et al. 2016

Int J Numerical Modelling

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Summary In this paper, the analog/radio frequency (RF) and linearity performance of an InAs‐based nanowire (NW) tunnel field‐effect transistor (TFET) is studied and compared with InAs‐based NW MSFET of identical dimension. InAs‐based NW TFETs shows a great promise for high performance digital application because of its superior subthreshold behavior. Different analog/RF and linearity key figure‐of‐merits like cut‐off frequency (ft) and 1‐dB compression point are extracted and the effect of gate length down scaling on those parameters has been studied. The results reveal that down scaled InAs‐based NW TFET shows a significant improvement in its RF and linearity performance. However, this advantage diminishes in terms of poor analog performance with gate‐length downscaling. This clearly indicates the necessity of a trade‐off between analog and RF performance. Moreover, an in‐depth comparison between InAs‐based NW TFET and conventional MOSFET has also been provided in order to demonstrate the superiority of InAs‐based NW TFET to become a competitive contender by replacing conventional MOSFET for Analog/Mixed signal System‐on‐Chip (SOC) applications. Copyright © 2016 John Wiley & Sons, Ltd.

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“…The probabilistic analyses of higher order derivatives are also important to study at scaled L G , the major issues that emphasize the analog and higher order derivatives are important for advance communication system. Non-linearity characteristics realizes unwanted disturbances with frequencies differences at input once, which generates Intermodulation Distortion (IMD) at output stage [13]- [15].…”

Section: Introductionmentioning

confidence: 99%

Impact of channel engineering (Si1-0.25Ge0.25) technique on GM(transconductance) and its higher order derivatives of 3D conventional and wavy Junctionless FinFETs (JLT)

et al. 2018

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The paper explores the analog analysis and higher order derivatives of drain current (I D ) at gate source voltage (V GS ), by introducing channel engineering technique of 3D conventional and Wavy Junctionless FinFETs (JLT) as silicon germanium (Si 1-0.25 Ge 0.25 ) device layer. In view of this, the performances are carried out for different gate length (L G ) values (15-30 nm) and current characteristics determined by maintaining constant ON current (I ON 10 -5 ) (A/μm) for both devices. With respect to this, a comparison has been made between these MOS structures at molefraction x = 0.25 and it was found that the electric field is perpendicular to the current flow which induces volume inversion approach. Accordingly, for the simulation study better channel controllability over the gate is observed for Wavy structures and high I D induces as the L G scales down. With respect to this the constant I ON determine I D , transconductance (g m ), transconductance generation factor (TGF) and its higher order terms (g \ m , and g \\ m ) of the devices are studied with relaxed SiGe approximation. The extensive simulation study on short channel (SC) parameters are also performed and it is observed that the Wavy JL FinFET shows less sensitivity towards short channel effects (SCEs) over conventional one, therefore the dependency of N-type doping concentration (N D = 1.7x10 19 cm -3 ) and metal workfunction (ϕ M = 4.6 eV) are responsible to achieving reduced SCEs.

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An Investigation of Linearity Performance and Intermodulation Distortion of GME CGT MOSFET for RFIC Design

Cited by 154 publications

References 20 publications

Impact of device parameter variation on RF performance of gate electrode workfunction engineered (GEWE)-silicon nanowire (SiNW) MOSFET

Impact of device parameter variation on RF performance of gate electrode workfunction engineered (GEWE)-silicon nanowire (SiNW) MOSFET

Effect of gate‐length downscaling on the analog/RF and linearity performance of InAs‐based nanowire tunnel FET

Impact of channel engineering (Si1-0.25Ge0.25) technique on GM(transconductance) and its higher order derivatives of 3D conventional and wavy Junctionless FinFETs (JLT)

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