An Introduction to High-Level Synthesis

Coussy, Philippe; Gajski, Daniel D.; Meredith, Michael P.; Takach, Andrés

doi:10.1109/mdt.2009.69

Cited by 325 publications

(116 citation statements)

References 18 publications

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“…Although scheduling and binding in high-level synthesis is a well-studied problem [15][16][17], many of those studies do not consider fault tolerance or error-correction percentage. More recent works have treated reliability as a primary concern in the high-level synthesis process but focus on different reliability goals in ASIC designs.…”

Section: Related Workmentioning

confidence: 99%

A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

Wilson

Shastri

Stitt

2017

International Journal of Reconfigurable Computing

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Computing systems with field-programmable gate arrays (FPGAs) often achieve fault tolerance in high-energy radiation environments via triple-modular redundancy (TMR) and configuration scrubbing. Although effective, TMR suffers from a 3x area overhead, which can be prohibitive for many embedded usage scenarios. Furthermore, this overhead is often worsened because TMR often has to be applied to existing register-transfer-level (RTL) code that designers created without considering the triplicated resource requirements. Although a designer could redesign the RTL code to reduce resources, modifying RTL schedules and resource allocations is a time-consuming and error-prone process. In this paper, we present a more transparent high-level synthesis approach that uses scheduling and binding to provide attractive tradeoffs between area, performance, and redundancy, while focusing on FPGA implementation considerations, such as resource realization costs, to produce more efficient architectures. Compared to TMR applied to existing RTL, our approach shows resource savings up to 80% with average resource savings of 34% and an average clock degradation of 6%. Compared to the previous approach, our approach shows resource savings up to 74% with average resource savings of 19% and an average heuristic execution time improvement of 96x.

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Section: Related Workmentioning

confidence: 99%

A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

Wilson

Shastri

Stitt

2017

International Journal of Reconfigurable Computing

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“…High Level Synthesis [11] is a design flow composed of a set of methodologies aimed at automatically generating an ASIC or FPGA implementation of a high level specification.…”

Section: The High Level Synthesismentioning

confidence: 99%

Computer assisted design and integration of FPGA accelerators in aerospace systems

Lattuada

Ferrandi

Perrotin

2016

2016 IEEE Aerospace Conference

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“…The Field-Programmable Gate Arrays (FPGA) offers a potential alternative to speed up the hardware realization (Coussy et al, 2009;Marufuzzaman et al, 2010;Reaz et al, 2011a). From the perspective of computer-aided design, FPGA comes with the merits of lower cost, higher density and shorter design cycle (Choong et al, 2005;Akter et al, 2008;Reaz et al, 2011b).…”

Section: Introductionmentioning

confidence: 99%

Single Core Hardware Module to Implement Boolean Function Classification Techniques

Marufuzzaman

Mamun²,

Hashim³

et al. 2011

American Journal of Applied Sciences

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Problem statement: Boolean function classification plays an important role in the field like technology mapping for digital circuit design, function mapping for minimization and the development of universal logic modules. Approach: In this study, we present a single core hardware module to implement Boolean function classification techniques on Altera FLEX10K FPGA device for lossless data compression. The compression algorithm was performed by incorporating Boolean function classification into Huffman coding. This allows compression that was more efficient because the data had been categorized and simplified before the encoding was done. Simulation, timing analysis and circuit synthesis were commenced to verify the functionality and performance of the designated circuits which supports the practicality, advantages and effectiveness of the proposed single core hardware implementation. Results: The result shows a higher compression ratio. The average compression ratio was 25-37.5% from numerous testing with various text inputs with a maximum clock frequency of 27.9 MHz. Conclusion: The hardware implementation demonstrated complete, correct functionality and met all the initial system requirements.

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An Introduction to High-Level Synthesis

Cited by 325 publications

References 18 publications

A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

Computer assisted design and integration of FPGA accelerators in aerospace systems

Single Core Hardware Module to Implement Boolean Function Classification Techniques

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