Computer assisted design and integration of FPGA accelerators in aerospace systems

Abstract

Abstract-The integration of Field Programmable Gate Arrays (FPGAs) in an aerospace system allows to improve its efficiency and its flexibility thanks to their programmability. To exploit these devices, the designer has to identify the functionalities that have to be executed on them and provide their implementation by means of Hardware Description Languages. Generating

Data Transfers Analysis in Computer Assisted Design Flow of FPGA Accelerators for Aerospace Systems

“…The information about the PDSs of the formal parameters has to be already available at the beginning of the analysis of a function because these parameters can be assigned to local variables or used as parameters of called functions. For this reason, caller functions have to be analyzed before called functions: the analysis of the whole application starts from main function (or from the entry point specified by the developer) and then all the other functions of the application are examined following one of the topological orders induced by the call graph (lines [2][3][4][5][6][7][8][9][10][11][12][13][14]. In presence of recursive calls, the functions in the corresponding strongly connected component have to be iteratively analyzed until the PDSs of their formal parameters do not change.…”

“…In [3] a design flow which partially addresses the issues of including FPGA hardware accelerators in a space system is presented. The design flow is based on the integration of High Level Synthesis methodologies in a framework [4] for the development of critical systems, but it is still semiautomatic: there are several steps that have to be performed by hand by the designer during the development of the solution.…”