An Integrated Pulse Width Modulator/Dead-time Generator with Improved Output Voltage Precision

Abstract

This paper presents an integrated pulse width modulator with dead-time generation capability. The proposed modulator can place proper dead-time around gating pulses while maintaining the correct volt-second of the output voltage on a pulse-by-pulse basis. The proposed method is suitable for digital implementation of the pulsewidth modulator (PWM). Compared to the conventional dead-time compensation by average voltage correction, the proposed method provides improved accuracy of output voltages and hence better dynamic response. Experimental results on a variable speed drive platform and a shunt active filter platform are provided to verify the proposed method. Comparisons with the conventional dead-time generation and compensation method on the same platforms are also presented. Fig. 1 shows a typical inverter switch pole with transistors T A1 , T A2 , and free wheeling diodes D 1 , D 2 . Dead-time is introduced between the gate signals of T A1 , and T A2 to avoid shorting the DC bus.During the dead-time the output voltage is determined by the polarity of the current, rather than the PWM gate signal. In order to maintain the correct timing and volt.-sec. of the output voltage pulse, the proposed scheme uses main PWM carrier T ri, and the auxiliary carriers T ri + and T ri − as illustrated in Fig. 2. For positive output current, ie. i > 0, the free-wheeling diode D 2 conducts during the dead-time, thus forcing the actual output voltage V AN to follow the ideal upper switch gate pulse V g10 . V g10 . So the actual gate pulse V g1 is generated by comparing V re f and T ri , and is maintained identical to V g10 . To place proper dead-time, V g2 is generated by comparing V re f and T ri− , so the dead-time T d is created between the actual gate pulses V g1 and V g2 as illustrated in Fig. 2. For negative output current, ie. i < 0, V re f is compared to T ri and T ri + to produce the gate pulses.The proposed integrated pulse-width modulator provides a solution to integrate the dead-time generator and the pulse-width modulator altogether. The proposed method is very convenient for digital implementation, as it is implemented on a CPLD in this paper. The proposed method produces output voltage pulses which are identical to the ideal gate pulses without any time delay. The dead-time placement also ensures the correctness of volt.-sec. on a per pulse basis. The proposed method is verified by a conventional V/ f inverter drive, and the motor current distortion is clearly improved.The shunt active filter test shows even more improvement in the precision of the current-controlled inverter. Non-memberHung-Chih Lin * Non-memberChung-Chuan Hou * Non-memberThis paper presents an integrated pulse width modulator with dead-time generation capability. The proposed modulator can place proper dead-time around gating pulses while maintaining the correct volt-second of the output voltage on a pulse-by-pulse basis. The proposed method is suitable for digital implementation of PWM, and the required computational resource is very low. Com...

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“…Fig. 4 shows the typical inverter switch pole with IGBT and free wheeling diodes (12) (13) . The IGBTs are driven by gate signals which are delayed by the dead time from ideal PWM signal.…”