An Integrated Memory Array Processor for Embedded Image Recognition Systems

Kyo, Shorin; Okazaki, Shinichiro; Arai, Tamio

doi:10.1109/tc.2007.1010

Cited by 19 publications

(14 citation statements)

References 30 publications

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“…After the image regions are stored in the external memory, they are read, line-by-line, into the internal memory to be processed in parallel using an approach somewhat similar to that used in [16,17], which is illustrated in Figure 3. During the rst r y iterations, the histograms for each column of the regions are computed.…”

Section: For Each Region R Imentioning

confidence: 99%

A parallel color-based particle filter for object tracking

Medeiros

Park

Kak

2008

2008 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops

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Porting well known computer vision algorithms to low power, high performance computing devices such as SIMD linear processor arrays can be a challenging task. One especially useful such algorithm is the color-based particle lter, which has been applied successfully by many research groups to the problem of tracking nonrigid objects. In this paper, we propose an implementation of the color-based particle lter suitable for SIMD processors. The main focus of our work is on the parallel computation of the particle weights. This step is the major bottleneck of standard implementations of the color-based particle lter since it requires the knowledge of the histograms of the regions surrounding each hypothesized target position. We expect this approach to perform faster in an SIMD processor than an implementation in a standard desktop computer even running at much lower clock speeds.

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Section: For Each Region R Imentioning

confidence: 99%

A parallel color-based particle filter for object tracking

Medeiros

Park

Kak

2008

2008 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops

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“…The limitations of [8] lie in the absence of a wide-word multiplier (due to a bit-serial architecture) and the 1 Mbit on-chip data memory, both of which reduce the overall performance when dataintensive video analysis applications are considered. While the architecture of [7] shows resemblance to our proposal, there are a number of significant differences, such as, the datapath resolution, the number of onchip compute units, the micro-architecture, the size of on-chip memory and the method of external stream interfacing. The processing elements in [7] operate in a 4-way very-long instruction word (VLIW) mode in contrast to the single-issue operation proposed here, a choice which has impact on the compiler development effort.…”

mentioning

confidence: 87%

“…At the extreme end, one finds massively-parallel SIMD (MP-SIMD) machines which try to exploit as much data-level parallelism as possible thereby maximizing the effective performance level [6][7][8]. The processor in [6], our first generation prototype, is realized in 180 nm CMOS technology and has limited compute power, small on-chip working memory and lacks support for instruction and task-level parallelism presented in this work.…”

mentioning

confidence: 99%

Xetal-II: A Low-Power Massively-Parallel Processor for Video Scene Analysis

Abbo

Kleihorst

Schueler

2009

J Sign Process Syst

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A processor architecture combining highperformance and low-power is presented. A prototype chip, Xetal-II, has been realized in 90 nm CMOS technology based on the proposed architecture. Recent experimental results show a compute performance of up to 140 GOPS at 785 mW when operating at 110 MHz. The main architectural feature that allows high computational efficiency is the massively-parallel single-instruction multiple-data (MP-SIMD) compute paradigm. Due to the high data-level parallelism, applications like video scene analysis can efficiently exploit the proposed architecture. The chip has an internal 16-bit datapath and 10 Mbit of on-chip video memory facilitating energy efficient implementation of video processing kernels.

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“…We propose an algorithm for an SIMD linear processor array architecture [19][20][21][22]. The Xetal family of SIMD processors, illustrated in Fig.…”

Section: Hardware Architecturementioning

confidence: 99%

“…4-similar approaches were used in [22,25]. This process is divided into two phases: vertical accumulation and horizontal accumulation.…”

Section: Parallel Histogram Computationmentioning

confidence: 99%

A parallel histogram-based particle filter for object tracking on SIMD-based smart cameras

Medeiros

Holguín

Shin

et al. 2010

Computer Vision and Image Understanding

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a b s t r a c tWe present a parallel implementation of a histogram-based particle filter for object tracking on smart cameras based on SIMD processors. We specifically focus on parallel computation of the particle weights and parallel construction of the feature histograms since these are the major bottlenecks in standard implementations of histogram-based particle filters. The proposed algorithm can be applied with any histogram-based feature sets-we show in detail how the parallel particle filter can employ simple color histograms as well as more complex histograms of oriented gradients (HOG). The algorithm was successfully implemented on an SIMD processor and performs robust object tracking at up to 30 frames per second-a performance difficult to achieve even on a modern desktop computer.

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An Integrated Memory Array Processor for Embedded Image Recognition Systems

Cited by 19 publications

References 30 publications

A parallel color-based particle filter for object tracking

A parallel color-based particle filter for object tracking

Xetal-II: A Low-Power Massively-Parallel Processor for Video Scene Analysis

A parallel histogram-based particle filter for object tracking on SIMD-based smart cameras

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