Xetal-II: A Low-Power Massively-Parallel Processor for Video Scene Analysis

Abbo, A.A.; Kleihorst, Richard; Schueler, B.

doi:10.1007/s11265-008-0332-1

Cited by 5 publications

(6 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In particular, the so-called smart cameras [1,15,22] integrate image processors capable of recognizing image patterns and making autonomous decisions. This sort of camera stands out from conventional cameras because of its low power consumption, high processing power, and autonomy.…”

Section: The Eye-ris Vision Systemmentioning

confidence: 99%

“…A ROF of rank r, denoted as ROF (r) , selects the r-th largest element from a list of pixel values defined by a structuring element. As r goes from 1 to N , where N is the number of elements, the filters ROF (1) and ROF (N ) correspond to the morphological dilation and erosion operators, respectively. Another special case occurs when r = (N + 1)/2, which corresponds to the median filter when N is an odd value.…”

Section: Rank-order Filter Implementation and Performancementioning

confidence: 99%

“…Also, this table shows that the number of erosions for r < 3 can be reduced by using the duality property [10], which states that ROF (r) (X) = ¬ROF (N −r+1) (¬X). Therefore, ROF (1) can be derived in terms of ROF (5) , while ROF (2) can be derived in terms of ROF (4) . In particular, the number of erosions N e using the duality property is computed as follows…”

Section: Implementation In the Eye-ris Vision Systemmentioning

confidence: 99%

See 2 more Smart Citations

Hierarchical stack filtering: a bitplane-based algorithm for massively parallel processors

Frias-Velazquez

Morros

García

et al. 2017

J Real-Time Image Proc

View full text Add to dashboard Cite

With the development of novel parallel architectures for image processing, the implementation of well-known image operators needs to be reformulated to take advantage of the so-called massive parallelism. In this work, we propose a general algorithm that implements a large class of nonlinear filters, called stack filters, with a 2D-array processor. The proposed method consists of decomposing an image into bitplanes with the bitwise decomposition and then processes every bitplane hierarchically. The filtered image is reconstructed by simply stacking the filtered bitplanes according to their order of significance. Owing to its hierarchical structure, our algorithm allows us to trade-off between image quality and processing time, and to significantly reduce the computation time of low-entropy images. Also, experimental tests show that the processing time of our method is substantially lower than that of classical methods when using large structuring elements. All these features are of interest to a variety of real-time applications based on morphological operations such as video segmentation and video enhancement.Peer ReviewedPostprint (author's final draft

show abstract

Section: The Eye-ris Vision Systemmentioning

confidence: 99%

Section: Rank-order Filter Implementation and Performancementioning

confidence: 99%

Section: Implementation In the Eye-ris Vision Systemmentioning

confidence: 99%

See 1 more Smart Citation

Hierarchical stack filtering: a bitplane-based algorithm for massively parallel processors

Frias-Velazquez

Morros

García

et al. 2017

J Real-Time Image Proc

View full text Add to dashboard Cite

show abstract

“…In [11]- [15], low price CMOS cameras and sensor nodes (Mica-X or self-developed motes) have been developed that have low power consumption and low latency, thereby improving the feasibility of practical WVSNs. There were a few attempts to apply energy harvesting to WVSNs and sensor networks in [16]- [18], although this work was limited to optimizing the performance of mote hardware for energy efficiency.…”

Section: A Related Workmentioning

confidence: 99%

A Pervasive Network Control Algorithm for Multicamera Networks

Lee

Kim

et al. 2014

IEEE Sensors J.

View full text Add to dashboard Cite

Abstract-Owing to the increasingly large volume and complexity of captured videos, renewable energy systems based on solar energy are of particular interest in the design of energy harvesting (EH) wireless visual sensor networks (WVSNs). Since additional energy consumption following image capture occurs owing to image processing, mote operation, data transmission, and reception, the capture rate significantly affects the lifetime of a node. To this end, we explore a novel energy-efficient framework for EH-WVSN design by developing an optimal algorithm named capture rate and pervasive network control for multicamera networks where the quality of service is maximized by obtaining optimal values for the capture rate, allocated energy, and transmit power, based on field of view-based networking in the presence of event and power acquisition patterns. Through simulations, we demonstrate the feasibility of EH-WVSNs in terms of energy consumption, energy allocation, and capture rate in a realistic scenario (parking surveillance).Index Terms-Capture rate, energy harvesting, visual sensor network, IEEE 802.15.4, field of view.

show abstract

“…In comparison to those processors, while exploiting the high-performance technologies of the multi-core architectures, the proposed processor is much more power efficient due to its use of fixed-point ALUs instead of floating-point ALUs as well as its use of 2-D direct memory access (DMA)-integrated NoC interfaces instead of a cache-based memory system that requires a power-hungry hierarchical memory architecture. Therefore, the processor can achieves higher computing power with lower power consumption compared to the multi-core processors [12], [13] and, also, SIMD-based parallel machines such as IMAPCAR and Xetal-II [14].…”

Section: B Related Workmentioning

confidence: 99%

A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams

Kim

Park

et al. 2013

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

Abstract-A heterogeneous multi-core processor is proposed to achieve real-time dynamic object recognition on HD 720p video streams. The context-aware visual attention model is proposed to reduce the required computing power for HD object recognition based on enhanced attention accuracy. In order to realize real-time execution of the proposed algorithm, the processor adopts a 5-stage task-level pipeline that maximizes the utilization of its 31 heterogeneous cores, comprising four simultaneous multithreading feature extraction clusters, a cache-based feature matching processor and a machine learning engine. Dynamic resource management is applied to adaptively tune thread allocation and power management during execution based on the detected amount of tasks and hardware utilization to increase energy efficiency. As a result, the 32 mm chip, fabricated in 0.13 m CMOS technology, achieves 30 frame/sec with 342 8-bit GOPS peak performance and 320 mW average power dissipation, which are a 2.72 times performance improvement and 2.54 times per-pixel energy reduction compared to the previous state-of-the-art.Index Terms-Multi-core processor, object recognition, scale invariant feature transform, heterogeneous, low power processor, dynamic resource management, dynamic voltage and frequency scaling. GLOSSARY OF ABBREVIATIONS GOPS

show abstract

Xetal-II: A Low-Power Massively-Parallel Processor for Video Scene Analysis

Cited by 5 publications

References 16 publications

Hierarchical stack filtering: a bitplane-based algorithm for massively parallel processors

Hierarchical stack filtering: a bitplane-based algorithm for massively parallel processors

A Pervasive Network Control Algorithm for Multicamera Networks

A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams

Contact Info

Product

Resources

About