An Integrated Linearization Technique for GaAs Bipolar WCDMA Power Amplifier

Rajendran, Jagadheswaran; Hamid, Sofiyah Sal; Mohd, Shukri Korakkottil Kunhi; Abdullah, Mohd Zaid; Ramiah, Harikrishnan; Kumar, Nagendra

doi:10.18520/cs/v114/i02/308-313

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“…In DPD, complex integration is a significant drawback. Nevertheless, the analog pre-distortion technique is preferred for linear PAs due to the preferred complexity relaxation and low cost of implementation (Rajendran et al, 2018;. Most analog predistortion linearizers cannot adjust amplitude modulation to amplitude modulation (AM-AM) and amplitude modulation to phase modulation (AM-PM) conversion separately, resulting in the difficulty to meet linearization requirement for AM-AM and AM-PM conversion simultaneously (Hu et al, 2011).…”

Section: Introductionmentioning

confidence: 99%

A fully matched dual stage CMOS power amplifier with integrated passive linearizer attaining 23 db gain, 40% PAE and 28 DBM OIP3

Gunasegaran

Rajendran

Mariappan

et al. 2021

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Purpose The purpose of this paper is to introduce a new linearization technique known as the passive linearizer technique which does not affect the power added efficiency (PAE) while maintaining a power gain of more than 20 dB for complementary metal oxide semiconductor (CMOS) power amplifier (PA). Design/methodology/approach The linearization mechanism is executed with an aid of a passive linearizer implemented at the gate of the main amplifier to minimize the effect of Cgs capacitance through the generation of opposite phase response at the main amplifier. The inductor-less output matching network presents an almost lossless output matching network which contributes to high gain, PAE and output power. The linearity performance is improved without the penalty of power consumption, power gain and stability. Findings With this topology, the PA delivers more than 20 dB gain for the Bluetooth Low Energy (BLE) Band from 2.4 GHz to 2.5 GHz with a supply headroom of 1.8 V. At the center frequency of 2.45 GHz, the PA exhibits a gain of 23.3 dB with corresponding peak PAE of 40.11% at a maximum output power of 14.3 dBm. At a maximum linear output power of 12.7 dBm, a PAE of 37.3% has been achieved with a peak third order intermodulation product of 28.04 dBm with a power consumption of 50.58 mW. This corresponds to ACLR of – 20 dBc, thus qualifying the PA to operate for BLE operation. Practical implications The proposed technique is able to boost up the efficiency and output power, as well as linearize the PA closer to 1 dB compression point. This reduces the trade-off between linear output power and PAE in CMOS PA design. Originality/value The proposed CMOS PA can be integrated comfortably to a BLE transmitter, allowing it to reduce the transceiver’s overall power consumption.

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Section: Introductionmentioning

confidence: 99%