An integrated CAD system for algorithm-specific IC design

Shung, C.B.; Jain, Rajeev; Rimey, Ken; Wang, E.; Srivastava, Mani; Richards, Brian; Lettang, E.; Azim, S.K.; Thon, L.E.; Hilfinger, Paul; Rabaey, Jan M.; Brodersen, R.W.

doi:10.1109/43.75628

Cited by 86 publications

(17 citation statements)

References 32 publications

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“…Fig. 9 shows another piece of Magic layout from the metal layer of a D flip-flop cell from the standard cell library in the Lager suite of CAD software [30]. The Integrated CAD Framework identifies two pairs of "open ends" and three occurrences of closely spaced "nested elbows" in the piece of layout shown in the figure.…”

Section: A Identification Of "Critical Features"mentioning

confidence: 99%

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Automated evaluation of critical features in VLSI layouts based on photolithographic simulations

Sengupta

Cavallaro

Wilson

et al. 1997

IEEE Trans. Semicond. Manufact.

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In this paper, we address the problem of identifying and evaluating "critical features" in an integrated circuit (IC) layout. The "critical features" (e.g., nested elbows and open ends) are areas in the layout that are more prone to defects during photolithography. As feature sizes become smaller (sub-micron range) and as the chip area becomes larger, new process techniques (such as, using phase shifted masks for photolithography), are being used. Under these conditions, the only means to design compact circuits with good yield capabilities is to bring the design and process phases of IC manufacturing closer. This can be accomplished by integrating photolithography simulators with layout editors. However, evaluation of a large layout using a photolithography simulator is time consuming and often unnecessary. A much faster and efficient method would be to have a means of automatically identifying "critical features" in a layout and then evaluate the "critical features" using a photolithography simulator. Our technique has potential for use either to evaluate the limits of any new and nonconventional process technique in an early process definition phase or in a mask house, as a postprocessor to improve the printing capability of a given mask. This paper presents a CAD tool (An Integrated CAD Framework) which is built upon the layout editor, Magic, and the process simulator, Depict 3.0, that automatically identifies and evaluates "critical features."

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Section: A Identification Of "Critical Features"mentioning

confidence: 99%

“…The piece of layout, evaluated in this section, was generated automatically by a router in the Lager suite of CAD software [30]. The wire routing which occurs between rows of standard cells is done using two metal layers (metal1 and metal2 in Magic).…”

Section: Application Of Phase Shifting To a Layout In Order To Achmentioning

confidence: 99%

Automated evaluation of critical features in VLSI layouts based on photolithographic simulations

Sengupta

Cavallaro

Wilson

et al. 1997

IEEE Trans. Semicond. Manufact.

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“…As they commonly have a bitsliced architecture [33], it should be possible to generate ALU's with such fault-tolerant design.…”

Section: Reconfigurationmentioning

confidence: 99%

Fault tolerant VLSI systems

Peercy

Banerjee

1993

Proc. IEEE

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This paper examines the wide variety of fault tolerance techniques applied to VLSl technology. We provide a brief synopsis of fault models at the device, gate, and function levels. Then, we introduce the basic methods available to the designer of fault tolerance measures by surveying redundancy techniques. The majority of this paper discusses fault detection, which is the discovery of a fault before it delivers errant data to the rest of the system. We examine techniques of fault detection that use space, time, and information redundancies. Along with these redundancy measures, we also investigate algorithm-based fault tolerance in VLSI components. After discussing large-scale processor-level implementations of fault detection, we describe fault tolerance in automated VLSl production systems.After our treatment of the detection of errors and faults, we examine the other areas of fault tolerance in VLSI: reconjiguration of the system and recovery of system operation. We look into the issues involved in reconjiguration after discover?/ of a fault in fabrication or in operation. Our time here is spent generally in VLSI arrays. We conclude our discussion offault tolerance in VLSl with an overview of the on-chip recovery capabilities of a VLSl microprocessor.

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“…The result of this step is a structural description in the sdl-language [Shu89], which serves as the input to the Lager IV assembly environment. The mapping process transforms the decorated flow graph into three structural subgraphs: the data path structure graph, the controller state machine graph, and the interface graph.…”

Section: Hardware Mappingmentioning

confidence: 99%

“…Next, a structural description is derived using some novel scheduling and hardware allocation algorithms. The final structm is then mapped into hardware (macro cells or gate arrays) and generated using the Lager IV silicon assembly system [Shu89]. Since high efficiency and optimal performance is a must, the HYPER system allows for user interference and entry at every level of abstraction.…”

Section: System Overviewmentioning

confidence: 99%