An integrated 60GHz low power two-chip wireless system based on IEEE802.11ad standard

Ma, Kaixue; Mou, Shouxian; Mahalingam, Nagarajan; Wang, Yisheng; Thangarasu, Bharatha Kumar; Yan, Jun; Ye, Wanxin; Wang, Keping; Lim, Wei Meng; Wong, T.; Lu, Yang; Yang, Wanlan; Yeo, Kiat Seng; Chin, F.; Peng, Xiaoming; Chai, Albert; Khiam-Boon, P. N. G.; Ho, Wong Sai; Keh, Raymond; Zhaohui, Cai; Zhang, Guoping; Yoong, Chee Piew; Khoi, Yin Jee; Zhang, Weiqiang; Xuhong, Qu; Yong, Law Sie; Zhao, Chuanqi; Simon, Chen Jian; Cho, Cheng Wang; Jayaraj, Raymond; Jin, Bo; Sun, Mengtao; Qing, Xianmin; Chen, Zhining

doi:10.1109/mwsym.2014.6848242

Cited by 13 publications

(5 citation statements)

References 9 publications

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“…The transceiver architecture of the proposed system is shown in Figure 3 [15]. It is a super-heterodyne transceiver with two stages of frequency conversion.…”

Section: System Architecturementioning

confidence: 99%

“…The divider chain in the PLL can be operated in the integer mode for better phase noise. The PLL employs a fractional frequency divider chain and can also support other reference frequencies between 33 MHz and 40 MHz or 100 MHz and 120 MHz [15]. To provide the mode switch between the different operation types, the LO network with a high-efficiency switch supports the LO power distribution to the transmitter chain, receiver chain, or both.…”

Section: Fdd and Fd Modes Of Operationmentioning

confidence: 99%

“…Some of the detailed sub-block circuit designs for the proposed transceiver are presented in previously published works [15,16,[24][25][26]. In this work, the proposed transceiver needs to additionally support FDD and FD operations.…”

Section: Design and Implementationmentioning

confidence: 99%

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A Full-Duplex 60 GHz Transceiver with Digital Self-Interference Cancellation

Wang,

Thangarasu,

Mahalingam

et al. 2024

Electronics

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This paper presents the design and measurement of an IEEE 802.11ad standard compatible RF transceiver for 60 GHz wireless communication systems. In addition to the traditional half-duplex (HD) mode, this work supports full-duplex (FD) operations to deliver better channel utilization and faster response times for the system. The isolation between the transmitter and receiver from the architecture design to system integration for FD operations has been fully considered. A digital self-interference cancellation (DSIC) is implemented in MATLAB to verify the FD performance. The super-heterodyne architecture with an intermediate frequency (IF) of 12 GHz is designed to suppress the image frequencies without using extra filters. A flexible phase-locked loop (PLL) synthesizer provides a local oscillator (LO) frequency with a 2 kHz resolution. Other than the time division duplex (TDD) mode used in the conventional 60 GHz system, a wide-bandwidth baseband digital variable-gain amplifier (DVGA) with a 3 dB bandwidth of more than 4 GHz also supports frequency division duplex (FDD) operations. The transceiver chip is fabricated using the Tower Jazz 0.18 µm SiGe BiCMOS process. With an on-board antenna, the transceiver covers all four channels in the 802.11ad standard, with MCS-12 (7.04 Gbps under 1.76 GSym/s and 16-QAM) under 1.5 m. In the proposed system design, the RF frontend-based self-interference (SI) suppression from the local transmitter to receiver LNA is around 54 dB. To achieve a practical FD application, the SI is further suppressed with the help of a digital SI compensation. The measured power consumption for the transmitter and receiver configurations are 194 mW and 231 mW, respectively, in HD mode and 398 mW for the FDD or FD operation mode.

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“…The transceiver architecture of the proposed system is shown in Figure 3 [15]. It is a super-heterodyne transceiver with two stages of frequency conversion.…”

Section: System Architecturementioning

confidence: 99%

Section: Fdd and Fd Modes Of Operationmentioning

confidence: 99%

See 1 more Smart Citation

A Full-Duplex 60 GHz Transceiver with Digital Self-Interference Cancellation

Wang,

Thangarasu,

Mahalingam

et al. 2024

Electronics

View full text Add to dashboard Cite

show abstract

“…The transceiver architecture of the proposed system is shown in Figure 3 [15,16]. It is a superheterodyne transceiver with two stages of frequency conversion.…”

Section: B System Architecturementioning

confidence: 99%

Full-Duplex 60GHz Transceiver with Digital Self-Interference Cancellation

Wang,

Thangarasu,

Mahalingam

et al. 2023

Preprint

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This paper presents the design and measurement of an IEEE 802.11ad standard compatible RF transceiver for 60GHz wireless communication system. In addition to the traditional half-duplex (HD) mode, this work supports full-duplex (FD) operation to deliver better channel utilization and faster response time for the system. The isolation between the transmitter and receiver from the architecture design to system integration for FD operation has been fully considered. A digital self-interference cancellation (DSIC) is implemented in MATLAB to verify the FD performance. The super-heterodyne architecture with an intermediate frequency (IF) of 12GHz is designed to suppress the image frequencies without using extra filters. A flexible phase-locked loop (PLL) synthesizer provides a local oscillator (LO) frequency with a 2kHz resolution. Other than the time division duplex (TDD) mode used in the conventional 60GHz system, a wide bandwidth baseband digital variable gain amplifier (DVGA) with a 3dB bandwidth of more than 4GHz also supports frequency division duplex (FDD) operation. The transceiver chip is fabricated in Tower Jazz 0.18µm SiGe BiCMOS process. With on-board antenna, the transceiver covers all four channels in 802.11ad standard with MCS-12 (7.04Gbps under 1.76GSym/s and 16-QAM) under 1.5m. In the proposed system design, the RF frontend based self-interference (SI) suppression from the local transmitter to receiver LNA is around 54dB. To achieve a practical FD application, the SI is further suppressed with the help of digital SI compensation. The measured power consumption for transmitter and receiver configuration is 194mW and 231mW, respectively, in HD mode and 398mW for FDD or FD operation mode.

show abstract

“…Integrated RF/millimeter-wave transceivers have been designed in the recent years with the latest state of the art offering a maximum supported throughput of 4.6Gbps using SiGe 0.18µm BiCMOS process. The total power consumption for transmission mode is 718mW and that of the receiving mode is 939mW [121],…”

Section: Motivationmentioning

confidence: 99%

An approach for circuit design optimization based on complexity considerations

Tan¹

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Optimizing circuit trade-offs is a highly challenging task for any design team. This challenge is further exacerbated with the additional design complexity of integrating multiple circuits. Today, with the increasing demand for newer wireless communication products, design teams face a shorter time-to-market (TTM) for every generation of their new products and each product requires major improvement in wireless capability. Hence, it is important for the design teams to design circuits with complexity in mind. A design approach divided into architecture complexity, component complexity and discretional complexity are proposed. A novel benchmarking figure-of-merit, complexity factor (CF), was formulated and proposed for the architecture complexity. A simulated application of a goal, gain optimization, demonstrated and revealed that a reduction of up to 400% in the normalized complexity factor (NCF) could enhance the gain performance by approximately up to 40% for ultra-high frequency (UHF) applications. As the number of variables to be permuted is very high for the power amplifier (PA) blocks from circuit down to the process level, it is treated as a black box in the analysis but the next topology complexity step addressed this. A topology comparison was proposed between a 2-stacked EDNFET and SGNFET and a 4-stacked resistorladder SGNFET PA. Both of them achieved a near 20dBm output power and approximately 60% efficiency on the test-chips measurements, which demonstrated that the 2-stacked EDNFET and SGNFET topology with a reduction in stack height is a potential candidate for a reduced difficulty and complexity Doherty power amplifier (DPA) design. In the discretional complexity step, we explored the linearization of the DPA and proposed a DPA with a gm3 cancellation bias scheme tapping on its intrinsic linearization property, without adding external circuity to XII increase the complexity of the overall circuit but at the same time, improve its linearity by 6-8dB compared to a DPA optimized for power and more than 9dB compared with a balance PA with a similar structure. XIII

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An integrated 60GHz low power two-chip wireless system based on IEEE802.11ad standard

Cited by 13 publications

References 9 publications

A Full-Duplex 60 GHz Transceiver with Digital Self-Interference Cancellation

A Full-Duplex 60 GHz Transceiver with Digital Self-Interference Cancellation

Full-Duplex 60GHz Transceiver with Digital Self-Interference Cancellation

An approach for circuit design optimization based on complexity considerations

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