A Full-Duplex 60 GHz Transceiver with Digital Self-Interference Cancellation

Abstract

This paper presents the design and measurement of an IEEE 802.11ad standard compatible RF transceiver for 60 GHz wireless communication systems. In addition to the traditional half-duplex (HD) mode, this work supports full-duplex (FD) operations to deliver better channel utilization and faster response times for the system. The isolation between the transmitter and receiver from the architecture design to system integration for FD operations has been fully considered. A digital self-interference cancellation (DSIC) is implemented in MATLAB to verify the FD performance. The super-heterodyne architecture with an intermediate frequency (IF) of 12 GHz is designed to suppress the image frequencies without using extra filters. A flexible phase-locked loop (PLL) synthesizer provides a local oscillator (LO) frequency with a 2 kHz resolution. Other than the time division duplex (TDD) mode used in the conventional 60 GHz system, a wide-bandwidth baseband digital variable-gain amplifier (DVGA) with a 3 dB bandwidth of more than 4 GHz also supports frequency division duplex (FDD) operations. The transceiver chip is fabricated using the Tower Jazz 0.18 µm SiGe BiCMOS process. With an on-board antenna, the transceiver covers all four channels in the 802.11ad standard, with MCS-12 (7.04 Gbps under 1.76 GSym/s and 16-QAM) under 1.5 m. In the proposed system design, the RF frontend-based self-interference (SI) suppression from the local transmitter to receiver LNA is around 54 dB. To achieve a practical FD application, the SI is further suppressed with the help of a digital SI compensation. The measured power consumption for the transmitter and receiver configurations are 194 mW and 231 mW, respectively, in HD mode and 398 mW for the FDD or FD operation mode.