An Integer Linear Programming Approach for Dedicated Machine Constraint

Pham, Huy; Shr, Arthur M. D.; Chen, P.P.

doi:10.1109/icis.2008.48

Cited by 4 publications

(1 citation statement)

References 23 publications

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“…Chung, Huang and Lee 2006). A MIP model primary focussing on this constraint is given by Pham, Shr and Chen (2008). Here the optimization objective is to find an order-layer-tool assignment minimizing a production cost function.…”

Section: Previous Related Workmentioning

confidence: 99%

A multistage mathematical programming based scheduling approach for the photolithography area in semiconductor manufacturing

Klemmt

Lange

Weigert

et al. 2010

Proceedings of the 2010 Winter Simulation Conference

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Facilities for wafer fabrication are one of the most complex manufacturing systems. Typically, the bottleneck of such facilities is the photolithography area because of its highly expensive tools and complex resource constraints. In this research, a multistage mixed integer programming based optimization approach for planning of such an area is presented. Thereby, several existing process constraints like equipment dedications, resist allocation, vertical dedications, mask availability are taken into account on the basis of different granularity levels. Altogether eleven different optimization models are presented within four different decomposition stages. Thereby, objected goals are the maximization of throughput, the minimization of setup costs and a balancing of machine utilization. On the basis of real manufacturing data the benefit of the proposed approach is evaluated within a first prototype. INTRODUCTION AND PROBLEM DESCRIPTIONThe planning and optimization of semiconductor manufacturing is a very complex task. Especially in the field of wafer processing -the so-called front-end -a lot of different processing steps are performed. These steps are for example typical batch tool operations like oven-and wet-etch processes, or typical cluster tool operations like dry-etch, implant or lithography processes. They have to be repeated to subsequently structure different layers of integrated circuits on the wafers (cf. Figure 1, left). Because of several workcenter-specific constraints and dependencies, these steps are hard to schedule. This is even more complex for facilities with concurrent business modes like production in parallel to research and development processes. That means a wider product mix and a potentially increased number of high-priority lots. As a consequence of complexity the overall scheduling problem is dissected. Also, workcenterspecific optimization approaches are developed. Usually the photolithography area is a bottleneck workcenter of a wafer fab because of its highly expensive machines and its complex process constraints (cf. Chung and Huang 2008). So, an effective planning of the photolithography area will have a high practical relevance for the whole fab. Generally, in this process a resist is structured to act as a direct mask for subsequent structuring of the underlying substrate material. The photolithography process comprises several sub-processes. Firstly, adhesives are added and moisture is removed from the surface. This is followed by a resist coating, the exposure process and the development of the resist. Finally, there is a curing and an inspection of the resist. The main photolithography process -the exposure -is depicted in Figure 1 (right). Thereby, a reticle (mask) is used to structure a resist layer with the desired circuit pattern. So, for every new layer with a changing pattern, the reticle has to be exchanged. Since integrated circuits are commonly created layer by layer, many cycles of 2474 978-1-4244-9865-9/10/$26.00 ©2010 IEEE

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Section: Previous Related Workmentioning

confidence: 99%