An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring

Chen, Yen‐Po; Jeon, D.; Lee, Yoonmyung; Kim, Yejoong; Foo, Zhiyoong; Lee, Inhee; Langhals, Nicholas B.; Kruger, Grant H.; Oral, Hakan; Berenfeld, Omer; Zhang, Zhengya; Blaauw, David; Sylvester, Dennis

doi:10.1109/jssc.2014.2364036

Cited by 150 publications

(28 citation statements)

References 23 publications

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“…The main benefit of such approach is that the impact of a person's motion and his daily activities is dramatically reduced. Chen et al [14] proposed a syringe-implantable ECG system for arrhythmia classification based on the state-of-the-art 65-nm CMOS process. The system acquires the ECG signal, filters it, amplifies it, and digitizes it through the analog front-end (AFE) module.…”

Section: A Literature Reviewmentioning

confidence: 99%

Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia

Bayasi¹,

Tekeste²,

Saleh³

et al. 2016

IEEE Trans. VLSI Syst.

108

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This paper presents the design of a fully integrated electrocardiogram (ECG) signal processor (ESP) for the prediction of ventricular arrhythmia using a unique set of ECG features and a naive Bayes classifier. Real-time and adaptive techniques for the detection and the delineation of the P-QRS-T waves were investigated to extract the fiducial points. Those techniques are robust to any variations in the ECG signal with high sensitivity and precision. Two databases of the heart signal recordings from the MIT PhysioNet and the American Heart Association were used as a validation set to evaluate the performance of the processor. Based on application-specified integrated circuit (ASIC) simulation results, the overall classification accuracy was found to be 86% on the out-of-sample validation data with 3-s window size. The architecture of the proposed ESP was implemented using 65-nm CMOS process. It occupied 0.112-mm 2 area and consumed 2.78-µW power at an operating frequency of 10 kHz and from an operating voltage of 1 V. It is worth mentioning that the proposed ESP is the first ASIC implementation of an ECG-based processor that is used for the prediction of ventricular arrhythmia up to 3 h before the onset.

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Section: A Literature Reviewmentioning

confidence: 99%

Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia

Bayasi¹,

Tekeste²,

Saleh³

et al. 2016

IEEE Trans. VLSI Syst.

108

View full text Add to dashboard Cite

show abstract

“…mm-scale imaging and motion detection system [3] (left) and pressure monitoring system [4] (right) Figure 4. mm-scale temperature sensing system [5] (left) and ECG monitoring SoC [6] (right) 978-1-4673-9308-9/15/$31.00 ©2015 IEEE -88 -ISOCC 2015…”

Section: Discussionmentioning

confidence: 99%

“…An electrocardiography (ECG) monitoring SoC [6] is designed for continuous arrhythmia monitoring. Thanks to aggressive noise optimization at the analog front-end and energy efficient detection algorithm implementation on digital processor, 64nW system power consumption was achieved.…”

Section: Ecg Monitoring Systemmentioning

confidence: 99%

“…This 'miniaturization' trend in electronics is best described by Bell's Law, which stated that a new class of smaller computers is developed approximately every decade by using fewer components or fractional parts of state-of-the-art computing systems [1]. With advances in low power design and packaging techniques, small sensing systems as small as a few cubic millimeters emerged recently [2] and prototypes have been demonstrated for a few different applications [3][4][5][6]. In this paper, such millimeter (mm)-scale sensors in recent literature are reviewed.…”

Section: Introductionmentioning

confidence: 99%

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A review of recent research on mm-scale sensor systems

Lee

2015

2015 International SoC Design Conference (ISOCC)

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“…Hence, a very high common mode rejection ratio (CMRR) is required. There have been several attempts to develop hardware for accurate ECG analysis and hardware and classification [3]. Fig.…”

Section: Ecg Analog Front-end Requirementsmentioning

confidence: 99%

A Low Noise Amplifier Suitable for Biomedical Recording Analog Front-End in 65nm CMOS Technology

Nagulapalli

Hayatleh

Barker

et al. 2019

J CIRCUIT SYST COMP

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This paper presents a fully integrated front-end, low noise amplifier (LNA), dedicated to the processing of various types of bio-medical signals, such as Electrocardiogram (ECG), Electroencephalography (EEG), Axon Action Potential (AAP). A novel noise reduction technique, for an operational transconductance amplifier (OTA), has been proposed. This adds a current steering branch parallel to the differential pair, with a view to reducing the noise contribution by the cascode current sources. Hence, this reduces the overall input-referred noise of the LNA, without adding any additional power. The proposed technique implemented in 65[Formula: see text]nm CMOS technology achieves 30 dB closed-loop voltage gain, 0.05[Formula: see text]Hz lower cut-off frequency and 100 MHz 3-dB bandwidth. It operates at 1.2[Formula: see text]V power supply and draws 1[Formula: see text][Formula: see text]A static current. The prototype described in this paper occupies 3300[Formula: see text][Formula: see text]m2 silicon area.

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An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring

Cited by 150 publications

References 23 publications

Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia

Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia

A review of recent research on mm-scale sensor systems

A Low Noise Amplifier Suitable for Biomedical Recording Analog Front-End in 65nm CMOS Technology

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